Abstract
Video coding techniques which are characterized by huge computational burden extensively consume power. Motion estimation with block matching criterion utilizing sum of absolute differences (SAD) with variable block size is the main source for such complexity and huge power consumption. In this work, we introduce a modified matching criterion in bit-level that lowers the computational complexity and hardware implementation when compared with the many SAD implementations introduced in the literature. We show that the number of hardware resources illustrated by the number of logic gates that are used in our design is much less than the number of the gates that are used in the traditional SAD and others in the literature. This leads in turn to a reduction in hardware complexity and consumed power. These are achieved by making our design rely on reusing the partial SAD values of smaller sub-blocks and then providing them to the compare and select unit as early as they are ready. Moreover, the final 41 motion vectors of motion estimation overlap in time and hence lower the number of output buses of the hardware implementation which results in a reduction in complexity as well. The video quality is only reduced by 0.17 dB while the bit-rate is increased only by 0.58 % in our simplified hardware architecture. The system logic synthesis is performed using the widely used FPGA platform. It produces 6.2 k LUT with a maximum operating frequency of 293 MHz (180 fps@CIF).
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References
Al-Najdawi N, Al-Najdawi MN, Tedmori S (2014) Employing a novel cross-diamond search in a modified hierarchical search motion estimation algorithm for video compression. Inf Sci 268:425–435
Asano S, Shun ZZ, Maruyama T (2010) An FPGA implementation of full-search variable block size motion estimation. In: Field-Programmable Technology (FPT), 2010 International Conference on (pp. 399–402). IEEE
Baek Y, Oh HS, Lee HK (1996) An efficient block-matching criterion for motion estimation and its VLSI implementation. IEEE Trans Consum Electron 42(4):885–892
Bahari A, Arslan T, Erdogan AT (2007) Reduced computation and memory access for VBSME using pixel truncation. In: SOC Conference, 2007 I.E. International (pp. 59–62). IEEE
Bahari A, Arslan T, Erdogan AT (2009) Low-power H. 264 video compression architectures for mobile communication. IEEE Trans Circ Syst Video Technol 19(9):1251–1261
Bergmann HC (1982) Displacement estimation based on the correlation of image segments. In: Int. Conf. on Electronic Image Processing
Celebi A, Lee HJ, Erturk S (2010) Bit plane matching based variable block size motion estimation method and its hardware architecture. IEEE Trans Consum Electron 56(3):1625–1633
Celebi A, Urhan O, Hamzaoglu I, Erturk S (2009) Efficient hardware implementations of low bit depth motion estimation algorithms. IEEE Signal Process Lett 16(6):513–516
Chatterjee SK, Chakrabarti I (2011) Power efficient motion estimation algorithm and architecture based on pixel truncation. IEEE Trans Consum Electron 57(4):1782–1790
Chen CY, Chien SY, Huang YW, Chen TC, Wang TC, Chen LG (2006) Analysis and architecture design of variable block-size motion estimation for H. 264/AVC. IEEE Trans Circ Syst I Regular Papers 53(3):578–593
Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification H.264 (V9) (2014) (http://handle.itu.int/11.1002/1000/12063)
Erturk S (2007) Multiplication-free one-bit transform for low-complexity block-based motion estimation. IEEE Signal Process Lett 14(2):109–112
Erturk A, Erturk S (2005) Two-bit transform for binary block motion estimation. IEEE Trans Circ Syst Video Technol 15(7):938–946
Feng J, Lo KT, Mehrpour H, Karbowiak AE (1995) Adaptive block matching motion estimation algorithm using bit-plane matching. In: Image processing, 1995. Proceedings, International Conference on (Vol. 3, pp. 496–499). IEEE
Gu M, Yu N, Zhu L, Jia W (2011) High throughput and cost efficient VLSI architecture of integer motion estimation for H. 264/AVC. J Comput Inf Syst 7(4):1310–1318
Hameed R, Qadeer W, Wachs M, Azizi O, Solomatnikov A, Lee BC, Horowitz M (2010) Understanding sources of inefficiency in general-purpose chips. In: ACM SIGARCH Computer Architecture News (Vol. 38, No. 3, pp. 37–47). ACM
Jain J, Jain A (1981) Displacement measurement and its application in interframe image coding. IEEE Trans Commun 29(12):1799–1808
Joint Video Team (JVT) reference software version 10.2
Kalaycioglu C, Ulusel OC, Hamzaoglu I (2009) Low power techniques for motion estimation hardware. In: Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on (pp. 180–185). IEEE
Le TM, Mason R, Panchanathan S (2000) Low complexity block motion estimation using morphological-based feature extraction and XOR operations. J Electron Imaging 9(2):110–116
Lee S, Kim JM, Chae SI (1998) New motion estimation algorithm using adaptively quantized low bit-resolution image and its VLSI architecture for MPEG2 video encoding. IEEE Trans Circ Syst Video Technol 8(6):734–744
Lee JH, Ra JB (2001) Efficient motion estimation using edge-based binary block-matching and refinement based on motion vector correlation. In: Image Processing, 2001. Proceedings. 2001 International Conference on (Vol. 2, pp. 957–960). IEEE
Li BM, Leong PH (2008) Serial and parallel FPGA-based variable block size motion estimation processors. J Signal Process Syst 51(1):77–98
Li R, Zeng B, Liou ML (1994) A new three-step search algorithm for block motion estimation. IEEE Trans Circ Syst Video Technol 4(4):438–442
Luo JH, Wang CN, Chiang T (2002) A novel all-binary motion estimation (ABME) with optimized hardware architectures. IEEE Trans Circ Syst Video Technol 12(8):700–712
Muralidhar P, Rao CR, Dwith CYN (2014) Efficient architecture for variable block size motion estimation in H. 264/AVC
Natarajan B, Bhaskaran V, Konstantinides K (1997) Low-complexity block-based motion estimation via one-bit transforms. IEEE Trans Circ Syst Video Technol 7(4):702–706
Ng KH, Po LM, Wong KM, Ting CW, Cheung KW (2009) Multiple block-size search algorithm for fast block motion estimation. In: Information, Communications and Signal Processing, 2009. ICICS 2009. 7th International Conference on (pp. 1–4). IEEE
Olivares J, Hormigo J, Villalba J, Benavides I, Zapata EL (2006) SAD computation based on online arithmetic for motion estimation. Microprocess Microsyst 30(5):250–258
Patras I, Hendriks EA, Lagendijk RL (2007) Probabilistic confidence measures for block matching motion estimation. IEEE Trans Circ Syst Video Technol 17(8):988–995
Porto MS, Sanchez G, Noble D, Agostini L, Bampi S (2011) An efficient ME architecture for high definition videos using the new MPDS algorithm. In: Proceedings of the 24th symposium on Integrated circuits and systems design (pp. 119–124). ACM
PowerPlay Early Power Estimator (EPE) and Power Analyzer. [online]. http://www.altera.com/support/devices/estimator/pow-powerplay.jsp
Richmond RS, Ha DS (2001) A low-power motion estimation block for low bit-rate wireless video. In: Low Power Electronics and Design, International Symposium on, 2001. (pp. 60–63). IEEE
Rong Y, Yu Q, An D, He Y (2013) Low power motion estimation based on non-uniform pixel truncation. In: Signal and Information Processing Association Annual Summit and Conference (APSIPA), 2013 Asia-Pacific (pp. 1–4). IEEE
Sampaio F, Zatt B, Shafique M, Agostini L, Bampi S, Henkel J (2013) Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding. In: Proceedings of the Conference on Design, Automation and Test in Europe (pp. 665–670). EDA Consortium
Song X, Chiang T, Lee X, Zhang YQ (2000) New fast binary pyramid motion estimation for MPEG2 and HDTV encoding. IEEE Trans Circ Syst Video Technol 10(7):1015–1028
Song CM, Guo Y, Wang XH, Liu D (2013) Fuzzy quantization based bit transform for low bit-resolution motion estimation. Signal Process Image Commun 28(10):1435–1447
Tran TH, Cho HM, Cho SB (2009) Performance enhancement of sum of absolute difference (SAD) computation in H. 264/AVC using saturation arithmetic. In: Emerging intelligent computing technology and applications (pp. 396–404). Springer Berlin Heidelberg
Vanne J, Aho E, Hamalainen TD, Kuusilinna K (2006) A high-performance sum of absolute difference implementation for motion estimation. IEEE Trans Circ Syst Video Technol 16(7):876–883
Vanne J, Aho E, Kuusilinna K, Hamalainen TD (2009) A configurable motion estimation architecture for block-matching algorithms. IEEE Trans Circ Syst Video Technol 19(4):466–477
Yeo H, Hu YH (1996) A novel architecture and processor-level design based on a new matching criterion for video compression. In: VLSI Signal Processing, IX, 1996, [Workshop on] (pp. 448–457). IEEE
Zhu C, Lin X, Chau LP, Lim KP, Ang HA, Ong CY (2001) A novel hexagon-based search algorithm for fast block motion estimation. In: Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP’01). 2001 I.E. International Conference on (Vol. 3, pp. 1593–1596). IEEE
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AlQaralleh, E.A., Abu-Sharkh, O.M.F. Low-complexity motion estimation design using modified XOR function. Multimed Tools Appl 75, 16809–16834 (2016). https://doi.org/10.1007/s11042-015-2948-z
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DOI: https://doi.org/10.1007/s11042-015-2948-z