Skip to main content
Log in

Experimental and theoretical investigation of bifurcated wafer warpage evolution in the wafer level packaging processes

  • Published:
Journal of Materials Science: Materials in Electronics Aims and scope Submit manuscript

Abstract

Wafer warpage, which mainly originated from thermal mismatch between the materials, has become serious in wafer level packaging (WLP) as larger diameter and thinner wafers are required currently. In this paper, three-dimensional wafer warpage profile and the warpage evolution during typical fan-in WLP processes including wafer thinning process were characterized in situ. Special attention was paid to the bifurcated phenomenon. Prior to the wafer thinning process, the wafer deformed into a bowl shape which was caused by polyimide (PI) curing. A distinct bifurcation behavior appeared and the wafer warped into a cylindrical shape when the wafer was thinned below 270 μm. This bifurcation behavior was systematically analyzed by theoretical analysis and finite element analysis (FEA). Equivalent material model method and perturbation method were employed to simplify the FEA model and incur the bifurcation behavior, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

References

  1. Y. Liu, Trends of power semiconductor wafer level packaging. Microelectron. Reliab. 50(4), 514–521 (2010)

    CAS  Google Scholar 

  2. R. Rongen, R. Roucou, P.J. vd Wels, F. Voogt, F. Swartjes, K. Weide-Zaage, Reliability of wafer level chip scale packages. Microelectron. Reliab. 54(9), 1988–1994 (2014)

    Google Scholar 

  3. E. Herth, S. Seok, N. Rolland, T. Lasri, Wafer level packaging compatible with millimeter-wave antenna. Sens. Actuators A 173(1), 238–243 (2012)

    CAS  Google Scholar 

  4. S. Seok, 9—Wafer-level packaging technology for RF MEMS A2—Uttamchandani, Handbook of mems for wireless and mobile applications (Woodhead Publishing, Deepak, 2013), pp. 258–290

    Google Scholar 

  5. M.-L. Huang, N. Zhao, S. Liu, Y.-Q. He, Drop failure modes of Sn–3.0Ag–0.5Cu solder joints in wafer level chip scale package. Trans. Nonferrous Metals Soc. China 26(6), 1663–1669 (2016)

    CAS  Google Scholar 

  6. K. Rongen, A. Mavinkurve, M. Chen, P.J. van der Wel, F.H.M. Swartjes, R.T.H. Rongen, Moisture absorption and desorption in wafer level chip scale packages. Microelectron. Reliab. 55(9), 1872–1876 (2015)

    Google Scholar 

  7. M. Topper, T. Fischer, T. Baumgartner, H. Reichl, A comparison of thin film polymers for wafer level packaging, electronic components and technology conference, 2010, pp. 769–776.

  8. S. Orain, J.C. Barbé, X. Federspiel, P. Legallo, H. Jaouen, FEM-based method to determine mechanical stress evolution during process flow in microelectronics, application to stress–voiding. Microelectron. Reliab. 47(2), 295–301 (2007)

    Google Scholar 

  9. S. Deng, S. Hwang, H. Lee, Warpage prediction and experiments of fan-out waferlevel package during encapsulation process. IEEE Trans. Compon. Packag. Manuf. Technol. 3(3), 452–458 (2013)

    Google Scholar 

  10. J. Lau, M. Li, Y. Lei et al., Warpage measurements and characterization of fan-out wafer-level packaging with large chips and multiple redistributed layers. IEEE Trans. Compon. Packag. Manuf. Technol. 8(10), 1729–1737 (2018)

    CAS  Google Scholar 

  11. F.X. Che, D. Ho, M.Z. Ding, D.R. Minwoo, Study on process induced wafer level warpage of fan-out wafer level packaging, Electronic Components and Technology Conference, 2016, pp. 1879–1885.

  12. H. Liu, Y. Liu, J. Ji, J. Liao, A. Chen, Y. Chen, N. Kao, Y. Lai, Warpage characterization of panel Fan-out (P-FO) package, electronic components and technology conference, 2014, pp. 1750–1754.

  13. A. Mallik, R. Stout, J. Ackaert, Finite-element simulation of different kinds of wafer warpages: spherical cylindrical, and saddle. IEEE Trans. Compon. Packag. Manuf. Technol. 4(2), 240–247 (2014)

    Google Scholar 

  14. C. Zhu, W. Ning, G. Xu, L. Luo, Stress evolution during thermal cycling of copper/polyimide layered structures. Mater. Sci. Semicond. Process. 27(Supplement C), 819–826 (2014)

    CAS  Google Scholar 

  15. <https://www.k-space.com/>).

  16. S.R. Oh, K. Yao, C.L. Chow, F.E.H. Tay, Residual stress in piezoelectric poly(vinylidene-fluoride-co-trifluoroethylene) thin films deposited on silicon substrates. Thin Solid Films 519(4), 1441–1444 (2010)

    CAS  Google Scholar 

  17. S. Gao, H. Huang, X. Zhu, R. Kang, Surface integrity and removal mechanism of silicon wafers in chemo-mechanical grinding using a newly developed soft abrasive grinding wheel. Materi. Sci. Semicond. Process. 63(Supplement C), 97–106 (2017)

    CAS  Google Scholar 

  18. S.S.L.B. Freund, Thin film materials: stress, defect formation and surface evolution (Cambridge University Press, Cambridge, 2004)

    Google Scholar 

  19. C.B. Masters, N.J. Salamon, Geometrically nonlinear stress-deflection relations for thin film/substrate systems. Int. J. Eng. Sci. 31(6), 915–925 (1993)

    CAS  Google Scholar 

  20. F.X. Che, H.Y. Li, X. Zhang, S. Gao, K.H. Teo, Wafer level warpage modeling methodology and characterization of TSV wafers, electronic components and technology conference, 2011, pp. 1196–1203.

Download references

Acknowledgements

The authors are grateful to Prof. Le Luo and Gaowei Xu from State Key Laboratory of Transducer Technology, SIMIT, China Academy of Sciences (CAS), for their help in theoretical calculation, wafer warpage measurement and useful discussions.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Chunsheng Zhu.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Zhu, C. Experimental and theoretical investigation of bifurcated wafer warpage evolution in the wafer level packaging processes. J Mater Sci: Mater Electron 31, 16531–16538 (2020). https://doi.org/10.1007/s10854-020-04207-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10854-020-04207-8

Navigation