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Combinational logic circuits based on a power- and area-efficient memristor with low variability

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Abstract

The saturation of complementary metal–oxide–semiconductor (CMOS) technology in terms of area and power efficiency has given rise to advanced research on nanodevices. Memristors and their switching properties facilitate the implementation of various combinational logics and neural networks by potential replacement of the existing CMOS technology for edge computing devices. This work presents the design, implementation, and performance evaluation of memristor-based combinational logic circuits including adders, subtractors, and decoders via MATLAB Simulink and Cadence Virtuoso. In this work, we propose an optimized design of memristor-based combinational logic circuits and conduct a comparative study with the conventional method. The proposed memristor model is thoroughly validated experimentally for a high-density Y2O3-based memristive crossbar array and shows ultralow values in device-to-device and cycle-to-cycle variability. The power calculated from these circuits is reduced by more than 90% as compared to conventional CMOS technology implemented in Cadence Virtuoso. Moreover, the number of components utilized in the memristor-based logic circuits is significantly reduced in comparison to existing CMOS technology, which makes it more area-efficient and opens new avenues for the design and implementation of complex logic circuitry in few-micrometer scale.

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Acknowledgements

Shruti Sandip Ghodke would like to thank Narendra Singh Dhakad for providing assistant on the Cadence Virtuoso platform to evaluate the 180-nm CMOS technology outcomes. This work is partially supported by CSIR (No. 22(0841)/20/EMR-II) and JSPS Invitational Fellowship award (ID: S23062).

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Authors and Affiliations

  1. Hybrid Nanodevice Research Group (HNRG), Department of Electrical Engineering, Indian Institute of Technology Indore, Simrol, Indore, Madhya Pradesh, 453552, India

    Shruti Sandip Ghodke & Shaibal Mukherjee

  2. School of Engineering, University of Edinburgh, Edinburgh, Scotland, UK

    Sanjay Kumar

  3. Centre for Advanced Electronics (CAE), Indian Institute of Technology Indore, Simrol, Indore, Madhya Pradesh, 453552, India

    Saurabh Yadav & Shaibal Mukherjee

  4. Nanoscale Devices, VLSI Circuit and System Design (NSDCS), Department of Electrical Engineering, Indian Institute of Technology Indore, Simrol, Indore, Madhya Pradesh, 453552, India

    Narendra Singh Dhakad

  5. School of Engineering, RMIT University, Melbourne, VIC, 3001, Australia

    Shaibal Mukherjee

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  1. Shruti Sandip Ghodke
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Correspondence to Sanjay Kumar or Shaibal Mukherjee.

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Ghodke, S.S., Kumar, S., Yadav, S. et al. Combinational logic circuits based on a power- and area-efficient memristor with low variability. J Comput Electron 23, 131–141 (2024). https://doi.org/10.1007/s10825-023-02117-6

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