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Design and implementation of a two-qubit quantum comparator circuit (Q-CC)

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Abstract

In this article, a two-qubit quantum comparator circuit (Q-CC) is proposed. The proposed circuit is implemented using Qiskit and is designed using a Peres gate, Feynman gate, and reversible NOT gate. The complexity of the output function is reduced using logic simplification. Hence, the number of gates used to design the proposed circuit is reduced, which in turn reduces the other parameters including quantum cost, garbage output, number of gates, constant input, and delay. The quantum cost, number of gates, and delay of the proposed circuit are 18, 8, and 5, which is an improvement of 16.66%, 20%, and 37.5%, respectively, with respect to previously reported results. The proposed reversible circuit is verified using the IBM Qiskit simulator.

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  1. Department of ECE, Pailan College of Management and Technology, Kolkata, West Bengal, 700104, India

    Heranmoy Maity

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  1. Heranmoy Maity
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Maity, H. Design and implementation of a two-qubit quantum comparator circuit (Q-CC). J Comput Electron 21, 530–534 (2022). https://doi.org/10.1007/s10825-022-01858-0

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