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Energy-efficient magnetic 5:2 compressors based on SHE-assisted hybrid MTJ/FinFET logic

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Abstract

Energy dissipation in integrated circuits has become a matter of grave concern. Various approaches at different levels of abstraction such as logic-in-memory structures based on magnetic tunnel junction (MTJ) devices and approximate computing can be employed to reduce energy consumption. Efficient hybrid MTJ/FinFET designs for exact and approximate 5:2 compressors are proposed herein. The proposed designs use the spin Hall effect (SHE)-assisted writing method to store data in MTJs, which significantly improves the energy efficiency of the MTJ switching as compared with the conventional spin transfer torque (STT) method. The circuits are simulated in HSPICE using 7-nm FinFET and SHE perpendicular MTJ models. The results indicate that the proposed approximate designs provide significant improvements in terms of energy consumption and device count compared with their exact counterpart. The first and second proposed approximate designs improve the power consumption by 51%, read delay by 16% and 26%, and transistor count by 63% and 70%, respectively, as compared with the exact design. The second approximate compressor offers a significantly lower error rate (27% versus 48%) in comparison with the first approximate design, as well as better performance parameters. The imprecise 5:2 compressors are used in image processing applications to assess their accuracy metrics. Comprehensive MATLAB simulations indicate that the proposed approach provides great capabilities for image processing applications considering various accuracy and quality metrics.

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References

  1. Sakellariou, P., Paliouras, V.: Application-specific low-power multipliers. IEEE Trans. Comput. 65(10), 2973–2985 (2016)

    Article  MathSciNet  Google Scholar 

  2. Razi, F., Moaiyeri, M.H., Rajaei, R., Mohammadi, S.: A variation-aware ternary spin-Hall assisted STT-RAM based on hybrid MTJ/GAA-CNTFET logic. IEEE Trans. Nanotechnol. 18(1), 598–605 (2019)

    Article  Google Scholar 

  3. Ghosh, B., Dey, R., Register, L.F., Banerjee, S.K.: A simulation study of voltage-assisted low-energy switching of a perpendicular anisotropy ferromagnet on a topological insulator. J. Comput. Electron. 16(1), 120–126 (2017)

    Article  Google Scholar 

  4. Gang, Y., Zhao, W., Klein, J.O., Chappert, C., Mazoyer, P.: A high reliability, low-power magnetic full adder. IEEE Trans. Magn. 47(11), 4611–4616 (2011)

    Article  Google Scholar 

  5. Thapliyal, H., Mohammad, A., Kumar, S.D., Sharifi, F.: Energy-efficient magnetic 4-2 compressor. Microelectron. J. 67, 1–9 (2017)

    Article  Google Scholar 

  6. Thapliyal, H., Mohammad, A., Sharifi, F., Kumar, S.D.: Energy-efficient design of hybrid MTJ/CMOS and MTJ/nanoelectronics circuits. IEEE Trans. Magn. 54(7), 1–8 (2018)

    Article  Google Scholar 

  7. Shafaei, A., Wang, Y., Pedram, M.: Low write-energy STT-MRAMs using FinFET-based access transistors. In: 2014 IEEE 32nd International Conference on Computer Design (ICCD) (2014)

  8. Sayyah Ensan, S., Moaiyeri, M.H., Ebrahimi, B., Hessabi, S., Afzali-Kusha, A.: A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology. J. Comput. Electron. 18(2), 519–526 (2019)

    Article  Google Scholar 

  9. Sharifi, F., Moaiyeri, M.H., Sharifi, H., Navi, K., Thapliyal, H.: On the design of quaternary arithmetic logic unit based on CNTFETs. Int. J. Electron. Lett. 7(1), 1–13 (2019)

    Article  Google Scholar 

  10. Xu, C., et al.: Impact of write pulse and process variation on 22 nm FinFET-based STT-RAM design: a device-architecture co-optimization approach. IEEE Trans. Multi-Scale Comput. Syst. 1(4), 195–206 (2015)

    Article  Google Scholar 

  11. Ansari, M.S., Jiang, H., Cockburn, B.F., Han, J.: Low-power approximate multipliers using encoded partial products and approximate compressors. IEEE J. Emerg. Sel. Top. Circuits Syst. 8(3), 404–416 (2018)

    Article  Google Scholar 

  12. Shirinabadi Farahani, S., Reshadinezhad, M.R.: A new twelve-transistor approximate 4: 2 compressor in CNTFET technology. Int. J. Electron. 106(5), 691–706 (2019)

    Article  Google Scholar 

  13. Ahmadinejad, M., Moaiyeri, M.H., Sabetzadeh, F.: Energy and area efficient imprecise compressors for approximate multiplication at nanoscale. AEU-Int. J. Electron. Commun. 110, 1–11 (2019)

    Article  Google Scholar 

  14. Liu, W., Xu, J., Wang, D., Wang, C., Montuschi, P., Lombardi, F.: Design and evaluation of approximate logarithmic multipliers for low power error-tolerant applications. IEEE Trans. Circuits Syst. I Regul. Pap. 65(9), 2856–2868 (2018)

    Article  Google Scholar 

  15. Maroufi, N., Bahrepour, D.: A novel three-input approximate XOR gate design based on quantum-dot cellular automata. Circuits Syst. Signal Process. 17(2), 866–879 (2018)

    Google Scholar 

  16. Chang, H., Gu, J., Zhang, M.: Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 51(10), 1985–1997 (2004)

    Article  Google Scholar 

  17. Sabetzadeh, F., Moaiyeri, M.H., Ahmadinejad, M.: A majority-based imprecise multiplier for ultra-efficient approximate image multiplication. IEEE Trans. Circuits Syst. I Regul. Pap. 66(11), 4200–4208 (2019)

    Article  Google Scholar 

  18. Gorantla, A., Deepa, P.: Design of approximate compressors for multiplication. ACM J. Emerg. Technol. Comput. Syst. 13(3), 44 (2017)

    Article  Google Scholar 

  19. Rostami, M., Mohanram, K.: Dual-Vth independent-gate FinFETs for low power logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3), 337–349 (2011)

    Article  Google Scholar 

  20. Gupta, S.K., Roy, K.: Low power robust FinFET-based SRAM design in scaled technologies. In: Circuit Design for Reliability, pp. 223–253 (2014)

  21. Zhao, W., Belhaire, E., Chappert, C., Mazoyer, P.: Spin transfer torque (STT)-MRAM–based runtime reconfiguration FPGA circuit. ACM Trans. Embed. Comput. Syst. 9(2), 14 (2009)

    Article  Google Scholar 

  22. Rajaei, R.: Radiation-hardened design of nonvolatile MRAM-based FPGA. IEEE Trans. Magn. 52(10), 1–10 (2016)

    Article  Google Scholar 

  23. van den Brink, A., et al.: Spin-Hall-assisted magnetic random access memory. Appl. Phys. Lett. 104(1), 012403 (2014)

    Article  Google Scholar 

  24. Wang, Z., Zhao, W., Deng, E., Klein, J.O., Chappert, C.: Perpendicular-anisotropy magnetic tunnel junction switched by spin-Hall-assisted spin-transfer torque. J. Phys. D Appl. Phys. 48(6), 065001 (2015)

    Article  Google Scholar 

  25. Deng, E., Wang, Z., Klein, J.O., Prenat, G., Dieny, B., Zhao, W.: High-frequency low-power magnetic full-adder based on magnetic tunnel junction with spin-Hall assistance. IEEE Trans. Magn. 51(11), 1–4 (2015)

    Google Scholar 

  26. Liang, J., Han, J., Lombardi, F.: New metrics for the reliability of approximate and probabilistic adders. IEEE Trans. Comput. 62(9), 1760–1771 (2013)

    Article  MathSciNet  Google Scholar 

  27. Clark, L., Vashishtha, V., Shifren, L., Gujja, A., et al.: ASAP7: A 7-nm FinFET predictive process design kit. Microelectron. J. 53, 105–115 (2016)

    Article  Google Scholar 

  28. Zhang, Y., Wang, X., Chen, Y.: STT-RAM cell design optimization for persistent and non-persistent error rate reduction: a statistical design view. In: Proceedings of the International Conference on Computer-Aided Design, pp. 471–477 (2011)

  29. Dorrance, R., Ren, F., Toriyama, Y., Hafez, A.A., Yang, C.-K.K., Markovic, D.: Scalability and design-space analysis of a 1 T-1 MTJ memory cell for STT-RAMs. IEEE Trans. Electron Devices 59(4), 878–887 (2012)

    Article  Google Scholar 

  30. Moaiyeri, M.H., Razi, F.: Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance. J. Comput. Electron. 16(2), 240–252 (2017)

    Article  Google Scholar 

  31. Wang, Z.: Compact modeling and circuit design based on ferroelectric tunnel junction and spin-Hall-assisted spin-transfer torque. Université Paris-Saclay, Paris (2015)

    Google Scholar 

  32. Priya, K.B., Sudarmani, R.: Performance analysis of Dadda multiplier using 5:2 compressor and its applications. Int. J. Adv. Inf. Sci. Technol. 5(4), 72–78 (2016)

    Google Scholar 

  33. Wang, Z., Bovik, A.C., Sheikh, H.R., Simoncelli, E.P.: Image quality assessment: from error visibility to structural similarity. IEEE Trans. Image Process. 13(4), 600–612 (2004)

    Article  Google Scholar 

  34. Akbari, O., Kamal, M., Afzali-Kusha, A., Pedram, M.: Dual-quality 4: 2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(4), 1352–1361 (2017)

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electrical Engineering, Shahid Beheshti University, G.C., 1983963113, Tehran, Iran

    Mohammad Ahmadinejad & Mohammad Hossein Moaiyeri

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  1. Mohammad Ahmadinejad
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  2. Mohammad Hossein Moaiyeri
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Correspondence to Mohammad Hossein Moaiyeri.

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Ahmadinejad, M., Moaiyeri, M.H. Energy-efficient magnetic 5:2 compressors based on SHE-assisted hybrid MTJ/FinFET logic. J Comput Electron 19, 206–221 (2020). https://doi.org/10.1007/s10825-019-01441-0

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