Abstract
An analytical center-potential-based threshold voltage model is developed for a symmetrical graded-channel dual-material double-gate strained-Si metal–oxide–semiconductor field-effect transistor (MOSFET) with interface charges by solving the two-dimensional (2-D) Poisson equation with suitable boundary conditions. The potential distribution of the device is determined by using the parabolic approximation method along the y-axis. This paper focuses mainly on the center-potential-based natural length to estimate the exact short-channel behavior of the device. Here, the leakage path is formed at the center rather than the surface of the channel. The proposed model is used to investigate the effects of different device parameters such as the strain in the Si channel, the channel length, and the thicknesses of the gate oxide and strained Si by performing extensive analysis on the center potential, threshold voltage, subthreshold swing, and short-channel effects. Considering its significance in the nanoscale regime, the hot-carrier-induced device degradation is also investigated. The proposed model is validated against numerical results obtained from technology computer-aided design (TCAD) simulations.
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Roldán, J.B., Gámiz, F.: Simulation and modelling of transport properties in strained-Si and strained-Si/SiGe-on-insulator MOSFETs. Solid-State Electron. 48(8), 1347–1355 (2004)
Vogelsang, T., Hofmann, K.R.: Electron mobilities and high-field drift velocities in strained silicon on silicon-germanium substrates. IEEE Trans. Electron Devices 39(11), 2641–2642 (1992)
Welser, J., Hoyt, J.L., Gibbons, J.F.: Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors. IEEE Electron Device Lett. 15(3), 100–102 (1994)
Lee, M.L., Fitzgerald, E.A.: Optimized strained Si/strained Ge dual-channel heterostructures for high mobility P- and N-MOSFETs. In: IEEE International Electron Devices Meeting 2003, pp. 18.1.1–18.1.4 (2003)
Takagi, S., Sugiyama, N., Mizuno, T., Tezuka, T., Kurobe, A.: Device structure and electrical characteristics of strained-Si-on-insulator (strained-SOI) MOSFETs. Mater. Sci. Eng. B: Solid-State Mater. Adv. Technol. 89(1–3), 426–434 (2002)
Drake, T.S., Chléirigh, C.N., Lee, M.L., Pitera, A.J., Fitzgerald, E.A., Antoniadis, D.A., Anjum, D.H., Li, J., Hull, R., Klymko, N., Hoyt, J.L.: Fabrication of ultra-thin strained silicon on insulator. J. Electron. Mater. 32(9), 972–975 (2003)
Ng, K.K., Taylor, G.W.: Effects of hot-carrier trapping in n- and p-channel MOSFETs. IEEE Trans. Electron Devices 30(8), 871–876 (1983)
Acovic, A., La Rosa, G., Sun, Y.-C.: A review of hot-carrier degradation mechanisms in MOSFETs. Microelectron. Reliab. 36(7–8), 845–869 (2002)
Ho, C.S., Huang, K.Y., Tang, M., Liou, J.J.: An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect. Microelectron. Reliab. 45(7–8), 1144–1149 (2005)
Liang, X., Taur, Y.: A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans. Electron Devices 51(9), 1385–1391 (2004)
Kang, H., Han, J., Choi, Y.: Analytical threshold voltage model for double-gate MOSFETs with localized charges. IEEE Electron Device Lett. 29(8), 927–930 (2008)
Baishya, S., Mallik, A., Sarkar, C.K.: A pseudo two-dimensional subthreshold surface potential model for dual-material gate MOSFETs. IEEE Trans. Electron Devices 54(9), 2520–2525 (2007)
Banerjee, P., Sarkar, S.K.: 3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects. J. Comput. Electron. 16(3), 631–639 (2017)
Saxena, M., Haldar, S., Gupta, M., Gupta, R.S.: Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency. IEEE Trans. Electron Devices 49(11), 1928–1938 (2002)
Goel, E., Kumar, S., Singh, K., Singh, B., Kumar, M., Jit, S.: 2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs. IEEE Trans. Electron Devices 63(3), 966–973 (2016)
Kumar, M.J., Venkataraman, V., Nawal, S.: Comprehensive approach to modeling threshold voltage of nanoscale strained silicon SOI MOSFETs. J. Comput. Electron. 6(4), 439–444 (2007)
Saha, P., Sarkhel, S., Dash, D.K., Senapati, S.: Advances in Communication. Devices and Networking, vol. 537. Springer, Singapore (2019)
Kumar, M.J., Venkataraman, V., Nawal, S.: A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs. IEEE Trans. Electron Devices 53(10), 2500–2506 (2006)
Kumar, M., Dubey, S., Tiwari, P.K., Jit, S.: Analytical modeling of threshold voltage of short-channel strained-Si on silicon-germanium-on-insulator (SGOI) metal-oxide-semiconductor field-effect transistors with localized charges. J. Comput. Theor. Nanosci. 11(1), 165–172 (2014)
Goel, E., Singh, B., Kumar, S., Singh, K., Jit, S.: Analytical threshold voltage modeling of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs. Indian J. Phys. 91(4), 383–390 (2017)
Colinge, J.-P., et al.: FinFETs and other multi-gate transistors, vol. 73. Springer, Berlin (2008)
Guide, Sentaurus Device User, Inc, Synopsys: Mountain View. CA, USA (2018)
Lim, J.-S., Thompson, S.E., Fossum, J.G.: Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs. IEEE Electron Device Lett. 25(11), 731–733 (2004)
Zhang, W., Fossum, J.G.: On the threshold voltage of strained-Si-Si1–xGex MOSFETs. IEEE Trans. Electron Devices 52, 263–268, 03 (2005)
Young, K.K.: Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans. Electron Devices 36(2), 399–402 (1989)
Omura, Y., Horiguchi, S., Tabe, M., Kishi, K.: Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs. IEEE Electron Device Lett. 14(12), 569–571 (1993)
Suzuki, K., Tanaka, T., Tosaka, Y., Horie, H., Arimoto, Y.: Scaling theory for double-gate SOI MOSFET’s. IEEE Trans. Electron Devices 40(12), 2326–2329 (1993)
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Suddapalli, S.R., Nistala, B.R. A center-potential-based threshold voltage model for a graded-channel dual-material double-gate strained-Si MOSFET with interface charges. J Comput Electron 18, 1173–1181 (2019). https://doi.org/10.1007/s10825-019-01377-5
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DOI: https://doi.org/10.1007/s10825-019-01377-5