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Circuit-level simulation of resistive-switching random-access memory cross-point array based on a highly reliable compact model

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Abstract

In this study, a simple, reliable, and universal circuit model of bipolar resistive-switching random-access memory (RRAM) is presented for the circuit-level simulation of a high-density cross-point RRAM array. For higher accuracy and reliability, the compact model has been developed to match the measurement data of the fabricated RRAM devices with \(\hbox {SiN}_{{x}}\) and \(\hbox {HfO}_{{x}}\) switching layers showing different reset switching behaviors. In the SPICE simulation, the RRAM cross-point array is virtually realized by embedding the empirically modeled memory cells, by which device performances such as read margin and power consumption in the high-density array are closely investigated.

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Acknowledgements

This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (2015R1A2A1A01007307) and in part by the Brain Korea 21 Plus Project in 2017.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center (ISRC), Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul, 08826, Republic of Korea

    Min-Hwi Kim, Sungjun Kim & Byung-Gook Park

  2. Samsung Electronics, 1 Samsungjeonja-ro, Hwaseong-si, Gyeonggi-do, 18848, Republic of Korea

    Kyung-Chang Ryoo

  3. Department of Electronics Engineering, Gachon University, 1342 Seongnamdaero, Sujeong-gu, Seongnam-si, Gyeonggi-do, 13120, Republic of Korea

    Seongjae Cho

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  1. Min-Hwi Kim
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  2. Sungjun Kim
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Correspondence to Byung-Gook Park.

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Kim, MH., Kim, S., Ryoo, KC. et al. Circuit-level simulation of resistive-switching random-access memory cross-point array based on a highly reliable compact model. J Comput Electron 17, 273–278 (2018). https://doi.org/10.1007/s10825-017-1116-2

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