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3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects

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Abstract

This paper presents a detailed study of the response of a new structure namely, high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual material bottom gate, towards various short channel effects, namely, drain-induced barrier lowering, threshold voltage roll-off, hot carrier effect and subthreshold swing. Based on the 3-D Poisson’s equation, the surface potential of the device is calculated along with its threshold voltage and electric field. The impact on the device performance due to the variation of different device parameters is also studied. The analytical results are verified using the simulated results obtained from ATLAS, a 3-D device simulator from SILVACO.

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Acknowledgements

Authors thankfully acknowledge the financial support obtained from UGC Vide File No. 43-293/2014 (SR).

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Authors and Affiliations

  1. Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, 700032, India

    Pritha Banerjee & Subir Kumar Sarkar

Authors
  1. Pritha Banerjee
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  2. Subir Kumar Sarkar
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Correspondence to Pritha Banerjee.

Appendix

Appendix

$$\begin{aligned} k_1= & {} \frac{\varepsilon _\mathrm{Ox} }{\varepsilon _\mathrm{Si} t_\mathrm{oxeff} }, \quad k_2 =\frac{\left( {1+\frac{C_{ox} }{C_\mathrm{Si} }+\frac{C_{Ox} }{C_b}} \right) }{t_\mathrm{{S-Si}} ^{2}\left( {1+\frac{2C_\mathrm{Si}}{C_b}} \right) }\\ k_3= & {} \frac{4}{w^{2}}k_1 , \quad k_4 =\frac{4}{w^{2}}k_2. \end{aligned}$$

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Banerjee, P., Sarkar, S.K. 3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects. J Comput Electron 16, 631–639 (2017). https://doi.org/10.1007/s10825-017-1002-y

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