Abstract
The purpose of this work is to propose a methodology to compute 1/f noise in MOS transistors under cyclo-stationary operation using the standard BSIM4 noise model. The proposed technique relies on a transient simulation, prior to the noise simulation, in which the average carrier quasi Fermi level in the channel is computed. Using this average quasi Fermi level and an energy distribution of traps, flicker noise parameters—NOIA, NOIB and NOIC—are recalculated in order to account for cyclo-stationary conditions. With these recalculated parameters, a noise simulation, using standard BSIM4 noise model, is performed. Simulation results are presented and compared to experimental data available in the literature, indicating the validity of the method.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Bloom, I., Nemirovsky, Y.: 1/f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulation. Appl. Phys. Lett. 58(15), 1664–1666 (1991)
Gierkink, S., Klumperink, E., van der Wel, A., Hoogzaad, G., van Tuijl, E., Nauta, B.: 1/f device noise reduction and its effects on phase noise in CMOS ring oscillators. IEEE J. Solid-State Circuits 34(7), 1022–1025 (1999)
Dierickx, B., Simoen, E.: The decrease of “random telegraph signal” noise in metal-oxide-semiconductor field-effect transistors when cycled from inversion to accumulation. J. Appl. Phys. 71, 2028–2029 (1992)
van der Wel, A., Klumperink, E., Hoekstra, E., Nauta, B.: Relating random telegraph signal noise in metal-oxide-semiconductor transistors to interface trap energy distribution. Appl. Phys. Lett. 87(18), 183507 (2005)
Klumperink, E., Gierkink, S., van der Wel, A., Nauta, B.: Reducing MOSFET 1/f noise and power consumption by switched biasing. IEEE J. Solid-State Circuits 35(7), 994–1001 (2000)
Siprak, D., Tiebout, T., Zanolla, N., Baumgartner, P., Fiegna, C.: Noise reduction in CMOS circuits through switched gate and forward substrate bias. IEEE J. Solid-State Circuits 44(7), 1959–1967 (2009)
Hung, K., Ko, P., Hu, Chenming, Cheng, Y.: A physics-based MOSFET noise model for circuit simulators. IEEE Trans. Electron Devices 37(5), 1323–1333 (1990)
Dallasen, R., Wirth, G.: Low frequency noise models analysis and simulation using Forward Bulk Bias. In: SBMicro, Curitiba, pp. 1–4 (2013)
Koh, J., Schmitt-Landsiedel, D., Thewes, R., Brederlow, R.: A complementary switched MOSFET architecture for the 1/f noise reduction in linear analog CMOS ICs. IEEE J. Solid-State Circuits 42(6), 1352–1361 (2007)
Wirth, G., da Silva, R., Kaczer, B.: Statistical model for MOSFET bias temperature instability component due to charge trapping. IEEE Trans. Electron Devices 58(8), 2743–2751 (2011)
Galup-Montoro, C., Schneider, M.: MOSFET Modeling and Analysis for Circuit Design. World Scientific, Singapore (2007)
van der Wel, A., Klumperink, E., Gierkink, S., Wassenaar, R., Wallinga, H.: MOSFET 1/f noise measurement under switched bias conditions. IEEE Trans. Electron Devices 21(1), 43–46 (2000)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Both, T.H., Wirth, G.I. & Vasileska, D. 1/f noise simulation in MOSFETs under cyclo-stationary conditions using SPICE simulator. J Comput Electron 14, 15–20 (2015). https://doi.org/10.1007/s10825-014-0655-z
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10825-014-0655-z