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A Power-Efficient Single Layer Full Adder Design in Field-Coupled QCA Nanocomputing

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Abstract

As an emerging technology device, Quantum-dot cellular automata (QCA) may be a suitable substitute for traditional semiconductor transistor technology. Arithmetic logic unit in field-coupled QCA has been also studied extensively in recent year. In this paper, the new low-power Exclusive-OR gate is presented, which is mainly based on QCA cellular leveled format. This Exclusive-OR gate can be used to design various useful QCA circuits. By using this gate, we design and implement a novel full adder circuit with low dissipation. The circuit is designed using only 45 normal cells in a single layer without crossover. Compared with previous designs, both decimal adders achieve better performance in terms of latency and overall cost. The operation of the proposed circuit has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared with previous designs in terms of power dissipation, cell-counts, area, latency and cost. The proposed full adder has the smallest area with less number of cells. And the total energy dissipation of our proposed full adder are only 0.05112 eV, 0.07454 eV and 0.10181 eV when tunneling energy levels are 0.5 Ek, 1 Ek and 1.5 Ek, respectively. The proposed single full adder also has the lowest total energy dissipation with a reduction of 20.94, 11.25 and 4.82% in 0.5 Ek, 1 Ek and 1.5 Ek tunneling energy levels, respectively when compared with the previous most power-efficient design.

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Acknowledgements

This research was supported by National Natural Science Foundation of China (No. 61271122).

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Correspondence to Lei Wang.

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Wang, L., Xie, G. A Power-Efficient Single Layer Full Adder Design in Field-Coupled QCA Nanocomputing. Int J Theor Phys 58, 2303–2319 (2019). https://doi.org/10.1007/s10773-019-04121-8

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  • DOI: https://doi.org/10.1007/s10773-019-04121-8

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