Skip to main content
SpringerLink
Log in

A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper proposes wide-range and fast locking all-digital delay-locked loop (WRADDLL) circuit with one cycle dynamic synchronizing. The WRADDLL not only synchronizes the input and output clocks in 5 clock cycles but maintains one cycle dynamic locking. The WRADDLL reduces the clock skew between the input and output clocks with three innovative techniques. First, by improving the mirror control circuit, the WRADDLL operates correctly with a flexible duty cycle clock signal. Second, the WRADDLL works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Besides, it can achieve one-cycle dynamic locking. Finally, the WRADDLL utilizes the band selector to achieve wide-range operation. After fine tuning, the maximum static phase error is less than 3% of clock cycle. The chip is fabricated by 90 nm standard CMOS process. Its operating frequency range is from 200 MHz to 2 GHz. The power consumption and RMS jitter are 3.24 mW and 1.49 ps at 2 GHz, respectively. The active area of this chip is 0.011 mm2.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21

Similar content being viewed by others

References

  1. Rehman, M. R. U., et al. (2020). A Design of 6.8 mW All digital delay locked loop with digitally controlled dither cancellation for TDC in ranging sensor. IEEE Access, 8, 57722–57732. https://doi.org/10.1109/ACCESS.2020.2982180

    Article  Google Scholar 

  2. Tsai, C.-W., Chiu, Y.-T., Tu, Y.-H., & Cheng, K.-H. (2021). A wide-range all-digital delay-locked loop for DDR1–DDR5 applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(10), 1720–1729. https://doi.org/10.1109/TVLSI.2021.3098171

    Article  Google Scholar 

  3. Hejazi, A., et al. (2020). A low-power multichannel time-to-digital converter using all-digital nested delay-locked loops with 50-ps resolution and high throughput for LiDAR sensors. IEEE Transactions on Instrumentation and Measurement, 69(11), 9262–9271. https://doi.org/10.1109/TIM.2020.2995249

    Article  Google Scholar 

  4. Chiu, W. H., Huang, Y.-H., & Lin, T. H. (2010). A dynamic phase error compensation technique for fast-locking phase-locked loops. IEEE Journal of Solid-State Circuits, 45(6), 1137–1149.

    Article  Google Scholar 

  5. Wang, J. S., Cheng, C. Y., Liu, J. C., Liu, Y. C., & Wang, Y. M. (2010). A duty-cycle-distortion-tolerant half-delay-line low-power fast-lock-in all-digital delay-locked loop. IEEE Journal of Solid-State Circuits, 45(5), 1036–1047.

    Article  Google Scholar 

  6. Saeki, T., Nakaoka, Y., Fujita, M., Tanaka, A., Nagata, K., Sakakibara, K., Matano, T., Hoshino, Y., Miyano, K., Isa, S., & Nakazawa, S. (1996). A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay. IEEE Journal of Solid-State Circuits, 31(11), 1656–1668.

    Article  Google Scholar 

  7. Sung, K., & Kim, L. S. (2004). A high-resolution synchronous mirror delay using successive approximation register. IEEE Journal of Solid-State Circuits, 39(11), 1997–2004.

    Article  Google Scholar 

  8. Cheng, K. H., Hong, K. W., Chen, C. H., & Liu, J. C. (2011). A high precision fast locking arbitrary duty cycle clock synchronization circuit. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(7), 1218–1228.

    Article  Google Scholar 

  9. Moon, S.-H., Haruhisa, I., Kim, K., Park, C. W., Chung, H. J., Kim, S. H., Kim, B. K., & Kim, O. (2015). Highly robust integrated gate-driver for in-cell touch TFT-LCD driven in time division driving method. IEEE Journal of Display Technology, 12(5), 435–441.

    Article  Google Scholar 

  10. Ito, D., Satou, K., Kitamura, K., Noto, T., Lee, A. Y., Shah, V. S., & Chen, J. Y. (2020). Synchronization technique of multi-chip cascade architecture for Automotive TDDI. Society for Information Display, 51, 1462–1465.

    Google Scholar 

  11. HSPICE User Guide: Analyzing electrical yields, Ver. C-2009.03, (2009).

  12. Hsiao, K. J., & Lee, T. C. (2009). An 8-GHz to 10-GHz distributed DLL for multiphase clock generation. IEEE Journal of Solid-State Circuits, 44(9), 2478–2487.

    Article  Google Scholar 

  13. AFahim, A. M. (2003). A compact, low-power low-jitter digital PLL. In Proc. European Solid-State Circuits Conference, Estoril (pp. 101-104)

  14. Choi, K.-H., Shin, J.-B., Sim, J.-Y., & Park, H.-J. (2009). An interpolating digitally-controlled oscillator for a wide-range all-digital PLL. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(9), 2055–2063.

    Article  MathSciNet  Google Scholar 

  15. Jung, D. H., An, Y. J., Ryu, K., Park, J. H., & Jung, S. O. (2015). All-digital fast-locking delay-locked loop using a cyclic-locking loop for DRAM. IEEE Transactions on Circuits and Systems II: Express Briefs, 62(11), 1023–1027.

    Google Scholar 

  16. Zhang, D. D., Yang, H. G., Zhu, W., Li, W., Huang, Z., Li, L., & Li, T. (2015). A multiphase DLL with a novel fast-locking fine-code time-to-digital converter. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(11), 2680–2684.

    Article  Google Scholar 

  17. Yao, C. Y., Ho, Y. H., Chiu, Y. Y., & Yang, R. J. (2015). Designing a SAR-based all-digital delay-locked loop with constant acquisition cycles using a resettable delay line. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(3), 567–574.

    Article  Google Scholar 

  18. Wang, J. S., Cheng, C. Y., Chou, P. Y., & Yang, T. Y. (2015). A wide-range, low-power, all-digital delay-locked loop with cyclic half-delay-line architecture. IEEE Journal of Solid-State Circuits, 50(11), 2635–2644.

    Article  Google Scholar 

  19. Hsieh, M. H., Chen, L. H., Liu, S. I., & Chen, C. P. (2016). A 6.7 MHz to 1.24 GHz 0.0318 mm2 fast-locking all-digital dll using phase-tracing delay unit in 90 nm CMOS. IEEE Journal of Solid-State Circuits, 51(2), 412–427.

    Article  Google Scholar 

  20. Bayram, E., Aref, A. F., Saeed, M., & Negra, R. (2018). 1.5–3.3 GHz, 0.0077 mm 2, 7 mW all-digital delay-locked loop with dead-zone free phase detector in 0.13 μm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(1), 39–50.

    Article  Google Scholar 

Download references

Acknowledgements

This work is provided by Industry-Academia Cooperation of Feng Chia University. The Chip fabrication was provided by Taiwan Semiconductor Research Institute (TSRI), Taiwan. The authors would like to thank Dr. Kuo-Hsing Cheng for paper revising. They would also like to thank the editor, associate editor, and reviewers who made this paper more fluent.

Author information

Authors and Affiliations

  1. Department of Electronic Engineering, Feng Chia University, Taichung, 40724, Taiwan

    Zhen-Jie Hong, Kuan-Yu Shen, Guan-Yu Chen & Wei-Ju Li

  2. Department of Electronic Engineering, National Kaohsiung Normal University, Kaohsiung, 82444, Taiwan

    Yu-Lung Lo

Authors
  1. Zhen-Jie Hong
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yu-Lung Lo
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Kuan-Yu Shen
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Guan-Yu Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Wei-Ju Li
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

Professor Hong is the main innovator of this paper. Professor Lo provided some ideas for this paper. Professor Hong and Professor Lo wrote the main manuscript text. Mr. Shen and Mr. Chen assisted in designing part of the circuit and simulation. Ms. Li is responsible for assisting with chip layout and measurement. All authors reviewed the manuscript.

Corresponding author

Correspondence to Yu-Lung Lo.

Ethics declarations

Competing interests

The authors declare no competing interests.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Hong, ZJ., Lo, YL., Shen, KY. et al. A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display. Analog Integr Circ Sig Process 118, 133–146 (2024). https://doi.org/10.1007/s10470-023-02192-6

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-023-02192-6

Keywords

Search

Navigation