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A soft-error resilient low power static random access memory cell

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Abstract

Advent and rapid development of on-chip computation in applications based on internet of things has opened space for integration of human life processes with technology. Wireless sensor node is a crucial component of this integration and SRAM employed in these nodes is under renovation phase. In this work, a novel single ended, bit-line powered 10T static random-access memory cell is proposed which improves access time, dissipates low power and supports bit-interleaving. The performance metrics of proposed design are compared with conventional 6T (conv.6T), tunable 8T(TUA8T), transmission gate based 9T(TRD9T), PPN10T(P10T), Schmitt-trigger based 10T (STR10T), loop cutting 10T (LC10T), and data dependent 11T(DD11T) cell to affirm the novelty of observed results. The reduction of soft error in proposed 10T cell is indicated by 1.22\(\times\)/1.13\(\times\)/1.13\(\times\)/0.91\(\times\)/1.49\(\times\)/1.12\(\times\) improvement in critical charge in comparison to conv.6T/TUA8T/TRD9T/STR10T/P10T/LC10T cell respectively. The read and write delay of proposed cell is improved by 1.56\(\times\)/1.04\(\times\)//1.04\(\times\)/1.57\(\times\)/1.14\(\times\) /1.12\(\times\)/1.05\(\times\) and 3.29\(\times\)/2.29\(\times\)/2.49\(\times\)/7.94\(\times\)/7.15\(\times\)/3.38\(\times\)/2.32\(\times\) respectively compared to conv.6T/TUA8T/TRD9T/STR10T/P10T/DD11T/LC10T cell. Additionally, read and write static noise margin of proposed 10T cell is improved by 2.22\(\times\)/2.04\(\times\)/1\(\times\)/1.67\(\times\)/1.06\(\times\)/1.75\(\times\)/1\(\times\) and 1.18\(\times\)/1.22\(\times\)/0.89\(\times\)/0.93\(\times\)/1.23\(\times\)/1.33\(\times\)/0.98\(\times\) respectively in comparison to conv. 6T/TUA8T/TRD9T/STR10T/P10T/DD11T/ LC10T cell. This article further demonstrates 1.88\(\times\) and 1.26\(\times\) tighter disperse in read power variability and read current variability respectively as compared with that of conv. 6T SRAM cell. The reduced cell density due to more number of transistors is compensated by improved \(I_{on}\)/\(I_{off}\) ratio.

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  1. Department of Electronics and communication Engineering, GLA University, Mathura, India

    Ashish Sachdeva & V. K. Tomar

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Sachdeva, A., Tomar, V.K. A soft-error resilient low power static random access memory cell. Analog Integr Circ Sig Process 109, 187–211 (2021). https://doi.org/10.1007/s10470-021-01898-9

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