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Design and implementation of a 60–113 GHz down-conversion mixer in 90 nm CMOS

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Abstract

A 60–113 GHz down-conversion mixer in 90 nm CMOS is demonstrated. The mixer adopts an RL core IF load, which is based on the series of a peaking inductor (L) and a parallel combination of the cross-coupled PMOS transistors (CCPT) and the diode-connected NMOS transistors (DCNT), i.e. L-CCPT–DCNT-based core IF load. Conversion gain (CG) can be significantly enhanced due to the increase of load impedance. The bandwidth can be improved due to the inductive peaking effect of the RL core IF load. The mixer consumes 3.2 mW and achieves RF-port input reflection coefficient of − 10 to − 31.2 dB for 82.8–97.2 GHz. The mixer attains CG of 16.8 ± 1.5 dB for 60–113 GHz. The corresponding 3 dB CG bandwidth is 53 GHz. Moreover, for 70–100 GHz, the mixer achieves CG of 17.4–18.3 dB and LO-RF isolation of 39.2–54.4 dB, one of the best CG and LO-RF isolation results ever reported for down-conversion mixers around 77 GHz or 94 GHz. These prominent results indicate that the down-conversion mixer is suitable for 77 GHz automobile radar and 94 GHz imaging radar systems.

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Acknowledgements

This work is supported by the Ministry of Science and Technology (MOST) of the R.O.C. under contracts MOST105-2221-E-260-025-MY3 and MOST106-2221-E-260-025-MY2. The authors are very grateful for the support from Taiwan Semiconductor Research Institute (TSRI), Taiwan, for chip fabrication and high-frequency measurement.

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  1. Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, ROC

    Yo-Sheng Lin & Kai-Siang Lan

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  1. Yo-Sheng Lin
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Correspondence to Yo-Sheng Lin.

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Lin, YS., Lan, KS. Design and implementation of a 60–113 GHz down-conversion mixer in 90 nm CMOS. Analog Integr Circ Sig Process 104, 109–119 (2020). https://doi.org/10.1007/s10470-020-01654-5

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