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A new step response modeling in CMOS operational amplifiers

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Abstract

Settling time is one of the most important parameters in opamps with feedback. In this article, the step response of the fully differential single stage folded cascade architecture amplifiers is analyzed to investigate the behavior of settling time and slew rate. An important characteristic of the proposed analytical model is that the behavior of the transistors is examined in detail after applying the step in the input, and it is shown that the settling time as well as slew rate would depend on the size of the input step. The resulting model can be beneficial for design and manual calculations in integrated circuits. Moreover, to examine the validity and precision of the resulting model, various simulations are performed, which show excellent matching between the proposed analytical model and the simulation results.

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References

  1. Wang, F., & Harjani, R. (1995). An improved model for the slewing behavior of opamps. IEEE Transactions on Circuits and Systems II, 42(10), 679–681.

    Article  Google Scholar 

  2. Yavari, M., Maghari, N., & Shoaei, O. (2005). An accurate analysis of slew rate for two-stage CMOS opamps. IEEE Transaction on Circuits and Systems II, 52(3), 164–167.

    Article  Google Scholar 

  3. Rezaee-Dehsorkh, H., Ravanshad, N., Lotfi, R., & Mafinezhad, Kh. (2009). Modified model for settling behavior of operational amplifiers in nanoscale CMOS. IEEE Transaction on Circuits and Systems II, 56(5), 384–388.

    Article  Google Scholar 

  4. Nairn, David G. (2012). Cascode loads and amplifier settling behavior. IEEE Transaction on Circuits and Systems I, 59(1), 44–51.

    Article  MathSciNet  Google Scholar 

  5. Yan, Z., Mak, P., Law, M., Martins, R., & Maloberti, F. (2015). Nested-current-mirror rail-to-rail-output single-stage amplifier with enhancements of DC gain, GBW and slew rate. IEEE Journal of Solid State Circuits, 50(10), 2353–2366.

    Article  Google Scholar 

  6. Seth, S., & Murmann, B. (2013). Settling time and noise optimization of a three-stage operational transconductance amplifier. IEEE Transaction on Circuits and Systems I, 60(5), 1168–1174.

    Article  MathSciNet  Google Scholar 

  7. Giustolisi, G., & Palumbo, G. (2015). Three-stage dynamic-biased CMOS amplifier with a robust optimization of the settling time. IEEE Transaction on Circuits and Systems I, 62(11), 2641–2651.

    Article  MathSciNet  Google Scholar 

  8. Chan Carusone, T., Johns, D. A., & Martin, K. W. (2012). Analog integrated circuit design (2nd ed.). New York: Wiley.

    Google Scholar 

Download references

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Authors and Affiliations

  1. Department of Electrical Engineering, Nour Branch, Islamic Azad University, Nour, Iran

    Hannane Gholamnataj, Habib Adarang, Seyed Saleh Mohseni & Seyed Saleh Ghoreishi

Authors
  1. Hannane Gholamnataj
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  2. Habib Adarang
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  3. Seyed Saleh Mohseni
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  4. Seyed Saleh Ghoreishi
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Correspondence to Habib Adarang.

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Gholamnataj, H., Adarang, H., Mohseni, S.S. et al. A new step response modeling in CMOS operational amplifiers. Analog Integr Circ Sig Process 101, 45–55 (2019). https://doi.org/10.1007/s10470-019-01485-z

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  • DOI: https://doi.org/10.1007/s10470-019-01485-z

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