Skip to main content
SpringerLink
Log in

A simple and high performance charge pump based on the self-cascode transistor

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

A novel charge pump for phase locked loops application based on the self-cascode (SC) transistor is presented. The proposed charge pump is simple and adds just a few number of transistors to basic charge pump circuit. The SC transistor is self-biased and has high output impedance and lower voltage headroom. Threshold voltage reduction method is used in SC transistor to reduce transistor size, increase the output resistance and help to improve the self-biased structure. The post layout simulation for the charge pump with SC transistor is performed using 180 nm CMOS technology. Based on the Monte Carlo process variation and corner case simulation a 2% current mismatch over the voltage range of 0.35–1.48 V is observed.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

Similar content being viewed by others

References

  1. Manikandan, R. R., & Amrutur, B. (2015). A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs. Microelectronics Journal, 46(6), 422–430. https://doi.org/10.1016/j.mejo.2015.03.004.

    Article  Google Scholar 

  2. Chuang, C. N., & Liu, S. I. (2007). A 0.5–5-ghz wide-range multiphase DLL with a calibrated charge pump. IEEE Journal of Solid-State Circuits, 54(11), 939–943. https://doi.org/10.1109/TCSII.2007.904155.

    Google Scholar 

  3. Fiorenza, J. K., Sepke, T., Holloway, P., Sodini, C. G., & Lee, H. S. (2006). Comparator-based switched-capacitor circuits for scaled CMOS technologies. IEEE Journal of Solid-State Circuits, 41(12), 2658–2668. https://doi.org/10.1109/JSSC.2006.884330.

    Article  Google Scholar 

  4. Johnson, M. G., & Hudson, E. L. (1988). A variable delay line PLL for CPU- coprocessor synchronization. IEEE Journal of Solid-State Circuits, 23(5), 1218–1223. https://doi.org/10.1109/4.5947.

    Article  Google Scholar 

  5. Charles, C. T., & Allstot, D. J. (2008). A buffered charge pump with zero charge sharing. In IEEE international symposium on circuits and systems (pp. 2633–2636). https://doi.org/10.1109/ISCAS.2008.4541997.

  6. Hwang, I. C., & Bae, S. G. (2009). Low-glitch, high-speed charge-pump circuit for spur minimization. Electronic Letters, 45(25), 1273–1274. https://doi.org/10.1049/el.2009.2660.

    Article  Google Scholar 

  7. Tsitouras, A., Plessas, F., Birbas, M., & Kalivas, G. (2011). A 1 V CMOS programmable accurate charge pump with wide output voltage range. Microelectronics Journal, 42(9), 1082–1089. https://doi.org/10.1016/j.mejo.2011.06.007.

    Article  Google Scholar 

  8. Larsson, P. (1999). A 2–1600 MHz CMOS clock recovery PLL with low Vdd capability. IEEE Journal of Solid-State Circuits, 34(12), 1951–1960. https://doi.org/10.1109/4.808920.

    Article  Google Scholar 

  9. Kaenel, V. V., Aebischer, D., Piguet, C., & Dijkstra, E. (1996). A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation. IEEE Journal of Solid-State Circuits, 31(11), 1715–1722. https://doi.org/10.1109/JSSC.1996.542316.

    Article  Google Scholar 

  10. Zhang, Z., Yang, J., Liu, L., Feng, P., Liu, J., & Wu, N. (2016). Source-Switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL. Electronic Letters, 52(14), 1211–1212. https://doi.org/10.1049/el.2016.1036.

    Article  Google Scholar 

  11. Cheng, S., Tong, H., Martinez, J. S., & Karsilayan, A. I. (2006). Design and analysis of an ultra high-speed glitch-free fully differential charge pump with minimum output current variation and accurate matching. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(9), 843–847. https://doi.org/10.1109/TCSII.2006.879100.

    Article  Google Scholar 

  12. Jiang, X., Zou, X., Xiao, D., & Liu, S. (2006). Self-balanced charge pump with very low phase error. Circuits System Signal Processing, 25(1), 111–124. https://doi.org/10.1007/s00034-005-0204-x.

    Article  MATH  Google Scholar 

  13. Lin, T. H., Ti, C. L., & Liu, Y. H. (2009). Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional- N PLLs. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(5), 877–885. https://doi.org/10.1109/TCSI.2009.2016180.

    Article  MathSciNet  Google Scholar 

  14. Huh, H., Koo, Y., Lee, K. Y., Ok, Y., Lee, S., Kwon, D., et al. (2004). A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump. In IEEE international solid-state circuits conference. https://doi.org/10.1109/ISSCC.2004.1332613.

  15. Liang, C. F., Chen, S. H., & Liu, S. I. (2008). A digital calibration technique for charge pumps in phase-locked systems. IEEE Journal of Solid-State Circuits, 43(2), 390–398. https://doi.org/10.1109/JSSC.2007.914283.

    Article  Google Scholar 

  16. Lee, J. S., Keel, M. S., Lim, S. I., & Kim, S. (2000). Charge pump with perfect current matching characteristics in phase-locked loops. Electronic Letters, 36(23), 1907–1908. https://doi.org/10.1049/el:20001358.

    Article  Google Scholar 

  17. Hwang, M. S., Kim, J., & Jeong, D. K. (2009). Reduction of pump current mismatch in charge-pump PLL. Electronic Letters, 45(3), 135–136. https://doi.org/10.1049/el:20092727.

    Article  Google Scholar 

  18. Joram, N., Wolf, R., & Ellinger, F. (2014). High swing PLL charge pump with current mismatch reduction. Electronic Letters, 50(9), 661–663. https://doi.org/10.1049/el.2014.0804.

    Article  Google Scholar 

  19. Cai, Q., Yang, Z., Zhang, M., Jia, X., & Fan, X. (2017). A fast-settling charge-pump PLL with constant loop bandwidth. Analog Integrated Circuits and Signal Processing, 94(1), 19–26. https://doi.org/10.1007/s10470-017-1083-3.

    Article  Google Scholar 

  20. Slieman, S. B., & Ismail, M. (2014). Dynamic self-regulated charge pump with improved immunity to PVT variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(8), 1716–1726. https://doi.org/10.1109/TVLSI.2013.2278375.

    Article  Google Scholar 

  21. Liu, P., Sun, P., Jung, J., & Heo, D. (2012). PLL charge pump with adaptive body-bias compensation for minimum current variation. Electronic Letters, 48(1), 16–18. https://doi.org/10.1049/el.2011.2835.

    Article  Google Scholar 

  22. Tanguay, L. F., Sawan, M., & Savaria, Y. (2009). A very-high output impedance charge pump for low-voltage low-power PLLs. Microelectronics Journal, 40(6), 1026–1031. https://doi.org/10.1016/j.mejo.2009.03.001.

    Article  Google Scholar 

  23. Choi, Y. S., & Han, D. H. (2006). Gain-Boosting charge pump for current matching in phase-locked loop. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(10), 1022–1025. https://doi.org/10.1109/TCSII.2006.882122.

    Article  Google Scholar 

  24. Fujimori, I., & Sugimoto, T. (1998). A 1.5 V 4.1 mw dual-channel audio delta-sigma D/A converter. IEEE Journal of Solid-State Circuits, 33(12), 1863–1870. https://doi.org/10.1109/4.735525.

    Article  Google Scholar 

  25. Beak, K. J., Gim, J. M., Kim, H. S., Na, K. Y., Kim, N. S., & Kim, Y. S. (2013). Analogue circuit design methodology using self-cascode structures. Electronic Letters, 49(9), 591–592. https://doi.org/10.1049/el.2013.0554.

    Article  Google Scholar 

  26. Xu, D., Liu, L., & Xu, S. (2016). High DC gain self-cascode structure of OTA design with bandwidth enhancement. Electronic Letters, 52(9), 740–742. https://doi.org/10.1049/el.2015.4017.

    Article  Google Scholar 

  27. Park, J. W., Choi, H., Choi, H. Y., & Kim, N. S. (2015). Two-stage feedback-looped charge-pump for spur reduction in CMOS PLL. Analog Integrated Circuits and Signal Processing, 83(2), 143–148. https://doi.org/10.1007/s10470-015-0517-z.

    Article  Google Scholar 

  28. Hati, M. K., & Bhattacharyya, T. K. (2013). A high o p resistance, wide swing and perfect current matching charge pump having switching circuit for PLL. Microelectronics Journal, 44(8), 649–657. https://doi.org/10.1016/j.mejo.2013.05.005.

    Article  Google Scholar 

  29. Shiau, M. S., Hsu, H. S., Cheng, C. H., Weng, H. H., Wu, H. C., & Liu, D. G. (2013). Reduction of current mismatching in the switches-in-source CMOS charge pump. Microelectronics Journal, 44(12), 1296–1301. https://doi.org/10.1016/j.mejo.2013.08.019.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Faculty of Electrical Engineering, Shahid Beheshti University, Tehran, Iran

    Mohsen Karbalaei Mohammad Ali & Omid Hashemipour

Authors
  1. Mohsen Karbalaei Mohammad Ali
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Omid Hashemipour
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Omid Hashemipour.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Karbalaei Mohammad Ali, M., Hashemipour, O. A simple and high performance charge pump based on the self-cascode transistor. Analog Integr Circ Sig Process 100, 633–638 (2019). https://doi.org/10.1007/s10470-019-01478-y

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-019-01478-y

Keywords

Search

Navigation