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Design considerations of CMOS active inductor for low power applications

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Abstract

Previous studies have shown that \(g_m/I_D\) (transconductance-to-drain-current) ratio based design is useful for optimizing analog circuits. In this paper, we explore challenges associated with designing a low-power active inductor. We focus in particular on sizing issues that arise as the transistor speed is maximized and the current consumption is minimized. Finally, we apply the results to design an amplifier integrated with an active inductor in \(0.18\,\upmu \hbox{m}\) CMOS process and show that by systematically working through sizing issues, a \(10\,\upmu \hbox{A}\) sub GHz amplifier can be designed.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, California State University Northridge, Northridge, CA, USA

    Jack Ou

  2. GeePs (UMR CNRS 8507), CentraleSuplec, Université Paris-Saclay, Gif-sur-Yvette, France

    Pietro M. Ferreira

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  1. Jack Ou
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  2. Pietro M. Ferreira
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Correspondence to Jack Ou.

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Ou, J., Ferreira, P.M. Design considerations of CMOS active inductor for low power applications. Analog Integr Circ Sig Process 94, 347–356 (2018). https://doi.org/10.1007/s10470-017-1059-3

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  • DOI: https://doi.org/10.1007/s10470-017-1059-3

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