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A simple circuit technique to relax the feedback timing of ΔΣ ADC for high-speed and high-accuracy applications

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Abstract

A novel and simple circuit technique to relax the feedback timing of input feed-forward ΔΣ analog-to-digital converter (ADC) is proposed for wideband and high-accuracy applications. The proposed method allows the use of low-speed comparator and DEM logic even for high-speed operation which helps to reduce the power consumption. A delta-sigma ADC with relaxed feedback timing was designed and simulated. The results verify the advantages of the proposed technique.

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Authors and Affiliations

  1. School of EECS, Oregon State University, 1148 Kelley Engineering Center, Corvallis, OR, 97331-5501, USA

    Youngho Jung & Gabor C. Temes

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  1. Youngho Jung
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  2. Gabor C. Temes
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Correspondence to Youngho Jung.

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Jung, Y., Temes, G.C. A simple circuit technique to relax the feedback timing of ΔΣ ADC for high-speed and high-accuracy applications. Analog Integr Circ Sig Process 92, 219–223 (2017). https://doi.org/10.1007/s10470-017-0993-4

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  • DOI: https://doi.org/10.1007/s10470-017-0993-4

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