A Computer-Aided Approach for Voltage Reference Circuit Design

Abstract

This work presents a computer-aided design (CAD) approach for voltage reference circuits by controlling main characteristics, such as temperature coefficient, power consumption, mismatch caused by the manufacturing process, transistor area and output noise. The CAD tool and the proposed methodology allow the designer to obtain accurate and optimum initial circuit sizing, thereby reducing the large number of computer runs usually required in voltage reference circuit designs. An illustrative example was carried out in a 180 nm CMOS process and verified by post layout simulations, whose results were in close agreement with the tool predictions, as shown in this paper. The reference circuit achieves an output voltage of 500 mV, a temperature coefficient of 15.19 ppm/$^\circ$C over the temperature range of -40 $^\circ$C to 100 $^\circ$C, a maximum quiescent current of 5 $\mu$A, a power supply rejection ratio of -57 dB, and a line regulation of 0.250 % from 1.2 V to 1.8 V supply voltage. The chip occupies an area of 0.072 mm$^2$.

Appendix - Mutual Compensation Approach

Using two CTAT generator circuits as shown in Fig. 3, we obtain CTAT voltages given by

$$\begin{aligned} V_{CTAT \ell }(T) = K_\ell \cdot V_{G4,\ell }(T) \ell =1,2 \end{aligned}$$

(28)

where

$$\begin{aligned} V_{G4,\ell }(T) = V_{Ton}(T)+\frac{k_BT}{q} \cdot n_n(T) \cdot F(i_{f4,\ell }) \ell =1,2 \end{aligned}$$

(29)

The mutual compensation can be derived assuming that $V_{CTAT2}(T)$ minus $V_{CTAT1}(T)$ does not change with temperature, which can be established by the conditions

$$\begin{aligned}&V_{CTAT2}(T_o) - V_{CTAT1}(T_o) = V_{IOAT} \end{aligned}$$

(30)

$$\begin{aligned}&\frac{\partial V_{CTAT2} (T_o)}{\partial T} - \frac{\partial V_{CTAT1} (T_o)}{\partial T} = 0 , \end{aligned}$$

(31)

where $V_{IOAT}$ is the desired output voltage and $T_o$ is the room temperature. Combining Eqs. (30) and (31), we obtain,

$$\begin{aligned}&K_2-K_1 = \frac{V_{IOAT}}{V_{Ton} - V'_{Ton}\cdot T_o} \end{aligned}$$

(32)

$$\begin{aligned}&K_2F_2-K_1F_1 = \frac{q }{n_nk_B} \cdot \frac{V'_{Ton} \cdot V_{IOAT}}{V'_{Ton}\cdot T_o-V_{Ton}} \end{aligned}$$

(33)

Now, fixing the gain $K_1$ and the function $F_1$ through the inversion level $i_{f1}$, as in Eq. (2), yields

$$\begin{aligned}&K_2 = \frac{K_1(V'_{Ton}T_o-V_{Ton})-V_{IOAT}}{V'_{Ton}T_o-V_{Ton}} \end{aligned}$$

(34)

$$\begin{aligned}&F_2 = \frac{K_1F_1(V'_{Ton}T_o-V_{Ton})+\frac{q}{n_nk_B}V_{IOAT}V'_{Ton}}{K_1(V'_{Ton}T_o-V_{Ton})-V_{IOAT}}. \end{aligned}$$

(35)

Therefore, by using the calculated values for $K_1$, $K_2$, $F_1$ and $F_2$, a mutual compensation (Eq. (13)) that generates the voltage $V_{IOAT}$ at the output of the reference is achieved.

The proposed technique based on the above equations takes advantage of the second term of Eq. (29), as follows. Since the thermal voltage ($k_BT/q$) has PTAT behavior and $F(i_f)$ increases monotonically with $i_f$ (see Fig. 15), the inversion level can be used to adjust the temperature influence according to Fig. 4. As illustrated in Fig. 16(a), an increase of the inversion level $i_{f4,2}$ makes it possible to reduce the temperature influence and increase the value of the voltage $V_{G4,2}$. Consequently, by multiplying $V_{G4,2}$ by the factor $K_2>1$, we can increase the temperature influence again, and create a voltage $V_{CTAT2}$, which decreases with the temperature at practically the same rate as that of the voltage $V_{CTAT1}$ (produced by $K_1 V_{G4,1}$). Finally, the difference between $V_{CTAT2}$ and $V_{CTAT1}$ yields $V_{IOAT}$ (Eq. (30)). $V_{IOAT}$. In Fig. 16(b) we present an illustrative numerical example in which fixing $V_{IOAT}$, $K_1$ and $F_1$, the required values of $K_2$ and $F_2$ are obtained. To reduce power consumption, $F_1$ should be as low as possible, which is limited by the value of $V_{G4,1}$ at maximum temperature, thereby ensuring the correct operation of $M_{4,1}$.

Fig. 15

Behavior of $F(i_f)$ according to the UICM model

Fig. 16

Diagram of the proposed technique to achieve the mutual compensation that takes advantage of the NMOS multi-threshold characteristics: (a) graphical representation; (b) numerical example