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Triple cascaded current-reuse low noise amplifier

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Abstract

A triple cascaded current-reuse CMOS low noise amplifier for 3.5 GHz WiMAX application is presented. Three common-source amplifiers are stacked and reuse the same current. This triple cascaded topology is able to enhance power gain but needs two coupling networks which costs enormous chip size. In order to have reasonable chip size, two coupling methods are investigated. For obtaining simultaneous input and noise matching, an additional capacitor is employed to adjust quality factor and reduce the gate induced current noise. The measurement results show a maximum power gain of 21.7 dB and minimum noise figure of 3.11 dB. The chip size is 1.05 mm \(\times\) 0.93 mm including all pads and the power consumption is 5.16 mW with a supply voltage of 1.5 V. A figure-of-merit of 49.7 is reached.

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Acknowledgments

The authors would like to thank the German Federal Ministry of Education and Research (BMBF) under Grant No. 03V023 “LeiCMOS”, National Science Council (NSC), Taiwan, and Chip Implementation Center (CIC), Taiwan for funding and implementing this work.

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Correspondence to Muh-Dey Wei.

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Wei, MD., Chang, SF. & Negra, R. Triple cascaded current-reuse low noise amplifier. Analog Integr Circ Sig Process 80, 327–333 (2014). https://doi.org/10.1007/s10470-014-0334-9

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  • DOI: https://doi.org/10.1007/s10470-014-0334-9

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