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Comparing controlled system synthesis and suppression enforcement

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  • Special Issue: RV 2019
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Abstract

Runtime enforcement and control system synthesis are two verification techniques that automate the process of transforming an erroneous system into a valid one. As both techniques can modify the behaviour of a system to prevent erroneous executions, they are both ideal for ensuring safety. In this paper, we investigate the interplay between these two techniques and identify control system synthesis as being the static counterpart to suppression-based runtime enforcement, in the context of safety properties.

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Authors and Affiliations

  1. Gran Sasso Science Institute, L’Aquila, Italy

    Luca Aceto

  2. Department of Computer Science, Reykjavík University, Reykjavík, Iceland

    Luca Aceto, Ian Cassar & Anna Ingólfsdóttir

  3. Department of Computer Science, University of Malta, Msida, Malta

    Ian Cassar & Adrian Francalanza

Authors
  1. Luca Aceto
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  2. Ian Cassar
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  3. Adrian Francalanza
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  4. Anna Ingólfsdóttir
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Correspondence to Ian Cassar.

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This work was partly supported by the projects “TheoFoMon: Theoretical Foundations for Monitorability” (nr.163406-051) and “Developing Theoretical Foundations for Runtime Enforcement” (nr.184776-051) of the Icelandic Research Fund, by the EU H2020 RISE programme under the Marie Skłodowska-Curie grant agreement nr. 778233, and by the Endeavour Scholarship Scheme (Malta), part-financed by the European Social Fund (ESF)—Operational Programme II—Cohesion Policy 2014-2020.

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Aceto, L., Cassar, I., Francalanza, A. et al. Comparing controlled system synthesis and suppression enforcement. Int J Softw Tools Technol Transfer 23, 601–614 (2021). https://doi.org/10.1007/s10009-021-00624-0

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