Abstract
A simple continuous analytical model is developed for the drain current of unipolar junction dual material double gate MOSFET (UJDMDG). The model is based on electrostatic potentials obtained from the solution of Poisson’s equation using parabolic approximation method, surface potential, electric field, threshold voltage roll-off and drain current are explicitly modelled. Analytical results are verified and validated by comparing it with the result obtained from Silvaco TCAD ATLAS device simulator making it suitable for circuit design simulations. A comparative study of the short-channel effects (SCEs) for UJDMDG and unipolar junction single material double gate MOSFET (UJSMDG) structures has been carried out in order to show the efficacy of gate material engineering to suppress SCEs. Moreover, the variation of RF and analog figure of merits as a function of downscaled gate lengths has been reported. To exhibit the superiority in RF/analog performance of UJDMDG over UJSMDG MOSFETs, the analog/RF performance parameters has been studied and compared for SoC applications.
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References
Abadi RMI, Ziabari SAS (2016) Representation of type I hetero structure junctionless tunnel field effect transistor for high performance logic application. Appl Phys A 122:616
Arora ND, Rios R, Huang CL, Raol K (1994) PCIM: a physically based continuous short-channel IGFET model for circuit simulation. IEEE Trans Electron Devices 41(6):988–997
Bentrcia T, Djeffal F, Chebaki E (2017) Approach for designing and modelling of nanoscale DG MOSFET devices using Kriging metamodeling technique. IET Circuits Devices Syst 11(6):618–623
Biswas K, Sarkar A, Sarkar CK (2018) Effect of varying Indium concentration of InGaAs channel on device and circuit performance of nanoscale double gate heterostructure MOSFET. Micro Nano Lett 13(5):690–694
Chakraborty A, Sarkar A (2015) Investigation of analog/RF performance of staggered heterojunctions based nanowire tunnelling field-effect transistors. Superlattices Microstruct 80:125–135
Chebaki E, Djeffal F, Hichem F, Bentrcia T (2016) Improved analog/RF performance of double gate junctionless MOSFET using both gate material engineering and drain/source extensions. Superlattices Microstruct 92:80–91
Chen YG, Kuo JB, Yu Z, Dutton RW (1995) An analytical drain current model for short-channel fully-depleted ultrathin silicon-on-insulator NMOS devices. Solid State Electron 38(12):2051–2057
Chiang T (2014) A novel scaling theory for fully depleted, multiple-gate MOSFET including effective number of gates (ENGs). IEEE Trans Electron Devices 61(2):631–633
Chiang TK (2016) A short-channel-effect-degraded noise margin model for junctionless double-gate MOSFET working on subthreshold CMOS logic gates. IEEE Trans Electron Device 63(8):2284–2289
Das TD, Pradhan R, Singh D, Rath A, Pattnaik S (2017) Performance analysis of devices in double gate MOSFET. Int J Eng Adv Technol (IJEAT) 7:131–136
Device simulator ATLAS User manual (2011) Silvaco Int., Santa Clara, CA [Online]
Ernst T, Cristoloveanu S, Ghibaudo G et al (2003) Ultimately thin double-gate SOI MOSFETs. IEEE Trans Electron Device 50:830–838
Ghosh D, Parihar MS, Armstrong GA, Kranti A (2012) High-performance junctionless MOSFETs for ultralow-power analog/RF applications. IEEE Electron Device Lett 33(10):1477–1479
Gupta S, Baishya S (2013) Analog and RF performance evaluation of dual metal double gate high-k stack (DMDG-HKS) MOSFETs. J Nano Electron Phys 5:30081–30088
Gupta A, Maurya N, Rai S (2017) Impact of dielectric pocket on analog/RF performance of short channel double gate MOSFET. In: 2017 4th International conference on power, control and embedded systems (ICPCES), Allahabad, pp 1–6
Hong S (2019) Compact charge modeling of double-gate MOSFETs considering the density-gradient equation. IEEE J Electron Devices Soc 7:409–416
ITRS (2009) International technology roadmap for semiconductors 2009 Edition and 2010 Update. http://www.itrs.net. Accessed 2018
Koley K, Syamal B, Kundu A, Mohankumar N, Sarkar CK (2012) Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions. Microelectron Reliab 52(11):2572–2578
Koley K, Dutta A, Saymal B, Saha SK, Sarkar CK (2013) Subthreshold analog/RF performance enhancement of underlap DG FETs with high-k spacer for low power applications. IEEE Trans Electron Devices 60(1):63–69
Lázaro A, Iñiguez B (2006) RF and noise performance of double gate and single gate SOI. Solid State Electron 50(5):826–842
Mohankumar N, Syamal B, Sarkar CK (2010) Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs. IEEE Trans Electron Devices 57(4):820–826
Narendar V, Girdhardas KA (2018) Surface potential modeling of graded-channel gate-stack (GCGS) high-K dielectric dual-material double-gate (DMDG) MOSFET and analog/RF performance study. Silicon 10:2865–2875
Nikoli MV, Radi SM, Mini V, Risti MM (1996) The dependence of the work function of rare earth metals on their electron structure. Microelectron J 27:93–96
Pati SK, Kole K, Dutta A et al (2014) Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs. Microelectron Reliab 54:1137–1142
Polishchuk I, Ranade P, Jae KT, Chenming H (2002) Dual work function metal gate CMOS transistors by Ni–Ti interdiffusion. IEEE Electron Device Lett 23(4):200–202
Pown M, Lakshmi B (2016) Investigation of ft and fmax in Si and Si1−x Gex based single and dual material double-gate tunnel FETs for RF applications. Adv Nat Sci Nanosci Nanotechnol 7:02500–02506
Ramezani Z, Orouji A (2018) Analysis and analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with N+–P− junction. J Comput Electron 17(2):670–681
Reddy GV, Kumar MJ (2005) A new dual material double gate (DMDG) nanoscale SOI MOSFET: two dimensional analytical modelling and simulation. IEEE Trans Electron Devices 4(2):260–268
Roldan JB, Gamiz F, Lopez-Villanueva JA, Carceller JE (1997) Modeling effects of electron velocity overshoot in a MOSFET. IEEE Trans Electron Devices 44(5):841–846
Roldan JB, Gamiz F, Lopez-Villanueva JA, Cartujo P, Carceller JE (1998) A model for the drain current of deep submicrometer MOSFET’s including electron-velocity overshoot. IEEE Trans Electron Devices 45(10):2249–2251
Roy NC, Gupta A, Rai S (2015) Analytical surface potential modeling and simulation of junctionless double gate (JLDG) MOSFET for ultra-low-power analog/RF circuits. Microelectron J 46(10):916–922
Sarkar A, Das AK, De S, Sarkar CK (2012) Effect of gate engineering in double-gate MOSFETs for analog/RF applications. Microelectron J 3:873–882
Sharan N, Mahapatra S (2014) A short-channel common double-gate MOSFET model adapted to gate oxide thickness asymmetry. IEEE Trans Electron Devices 61(8):2732–2737
Sharma RK, Bucher M (2012) Device design engineering for optimum analog/RF performance of nanoscale DG MOSFETs. IEEE Trans Nanotechnol 11(5):992–998
Suzuki K, Sugii T (1995) Analytical models for n+–p+ double gate SOI MOSFETs. IEEE Trans Electron Devices 42(11):1940–1948
Swain SK, Dutta A, Adak S et al (2016) Influence of channel length and high-k oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DGMOSFETs. Microelectron Reliab 61:24–29
Taur Y, Choi W, Zhang J, Su M (2019) A non-GCA DG MOSFET model continuous into the velocity saturation region. IEEE Trans Electron Devices 66(3):1160–1166
Ward DE, Dutton RW (1978) A charge-oriented model for MOS transistor capacitances. IEEE J Solid State Circuits 13(5):703–708
Woo J, Choi J, Choi Y (2013) Analytical threshold voltage model of junctionless double-gate MOSFETs with localized charges. IEEE Trans Electron Devices 60(9):2951–2955
Yeo YC, King TJ, Hu C (2003) MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations. IEEE Trans Electron Device 50(4):1027–1035
Young KK (1989) Short-channel effects in fully depleted SOI MOSFETs. IEEE Trans Electron Device 36(2):399–402
Zhou X, Long W (1998) A novel hetero-material gate (HMG) MOSFET for deep submicron ULSI technology. IEEE Trans Electron Device 45:2546–2548
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Basak, A., Chanda, M. & Sarkar, A. Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications. Microsyst Technol 27, 3995–4005 (2021). https://doi.org/10.1007/s00542-019-04691-x
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DOI: https://doi.org/10.1007/s00542-019-04691-x