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Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders

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Abstract

Ternary logic has received substantial attention over binary logic due to diminished delay, reduced power consumption, and minimized area requirements. Carbon Nanotube Field Effect Transistors (CNTFETs) are mostly preferred for the implementation of ternary logic because of their ability to achieve multi-threshold transistors. This paper presents an energy-efficient CNTFET-based 3-trit Wallace tree multiplier design using a novel 4-input ternary adder (called 4-ITA), full-adder, and half-adder. We have proposed half-adder, full-adder, and 1-trit multipliers using a new 3:1 multiplexer module (called MUX-2) that significantly enhances energy efficiency within our ternary multiplier design. This multiplexer, leveraging high and standard threshold voltage devices, greatly optimizes our ternary multiplier’s power consumption and computational speed. Furthermore, we reduced power dissipation by minimizing switching transitions within the signal generation circuits of both MUX-2 and the arithmetic modules. All the arithmetic designs were designed using the 45 nm CNTFET technology. Results prove that the 3-trit multiplier achieved 40% lesser power consumption and a 51% power delay product improvement compared to the best literature design.

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Authors and Affiliations

  1. Department of Electrical and Electronics Engineering, BITS Pilani, Hyderabad Campus, Hyderabad, India

    Aalelai Vendhan, Syed Ershad Ahmed & S. Gurunarayanan

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  1. Aalelai Vendhan
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  2. Syed Ershad Ahmed
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  3. S. Gurunarayanan
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Contributions

AV: Conceptualization, Methodology, Analysis, Writing—Orginal Draft. SEA: Resources, Validation, Writing—Review & Editing. SG: Supervision, Resources, Validation, Writing—Review & Editing.

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Correspondence to S. Gurunarayanan.

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Vendhan, A., Ahmed, S.E. & Gurunarayanan, S. Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders. Circuits Syst Signal Process (2024). https://doi.org/10.1007/s00034-024-02659-5

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