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An 18-bit SAR ADC with Mixed DAC and Capacitive Recombination Calibration

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Abstract

This paper presents a high-resolution 18-bit SAR ADC with a high 10-bit capacitor DAC and a low 8-bit resistor DAC. The total required number of the unit capacitors is decreased to 512. Foreground digital calibration based on capacitive recombination is introduced to improve linearity. Preamplifiers and output offset storage(OOS) enhance the noise and offset performance of the comparator. As a result, the design under 180 nm process achieves a signal-to-noise and distortion ratio(SNDR) of 105.5dB and a spurious-free dynamic range (SFDR) of 116.3dB under 1 MS/s sampling rate with a single channel. The effective number of bits (ENOB) can reach 17.23 bits with a Nyquist-rate input while consuming 46 mW from a 5 V supply. The resultant Schreier and Walden figures of merit (FoM) are 178.92 dB and 295.34 fJ/conversion-step, respectively. The proposed SAR ADC occupies an actual area of 3850 \(\upmu \)m by 2810 \(\upmu \)m.

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Correspondence to Hua Fan or Qi Wei.

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The work of Hua Fan was supported by Sichuan Science and Technology Program under Grant 2022YFG0164 and supported by Medico-Engineering Cooperation Funds from University of Electronic Science and Technology of China under Grant ZYGX2021YGLH203, and supported by general project of Chongqing Natural Science Foundation under Grant 2022NSCQ-MSX5348, and supported by Guangdong Basic and Applied Basic Research Foundation under Grant 2023A1515010041.

The work of Quanyuan Feng was supported by the Important Project of the National Natural Science Foundation of China under Grant 62090012.

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Li, D., Li, Z., Chen, Z. et al. An 18-bit SAR ADC with Mixed DAC and Capacitive Recombination Calibration. Circuits Syst Signal Process (2024). https://doi.org/10.1007/s00034-024-02610-8

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