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FPGA Design and Implementation of Improved DFxLMS Algorithm for Compressor Noise Cancellation System

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Abstract

To improve the convergence speed and noise cancellation performance of the Delayed Filtered-x Least Mean Square (DFxLMS) algorithm in the hardware implementation of compressor noise cancellation system, an improved Delayed Filtered-x Least Mean Square algorithm based on field-programmable gate array (FPGA) is proposed. The algorithm uses a parallel finite impulse response (FIR) filter structure and DSP48E1 module to implement the parallel multiplication and addition operation, which decreases hardware resource consumption and increases the system’s processing speed. The cut set retiming technique reallocates the location of delay units to streamline the algorithm structure, reduce the critical path delay and increase the system data throughput. Moreover, through the adaptive filtering of input and feedback signals of the filter module, the noise suppression effect of the algorithm is improved. The results show that the maximum noise cancellation of the algorithm is 10 dB in the compressor noise cancellation system, which is 3 dB higher than the DFxLMS algorithm, and has 1.5 times higher data throughput. In addition, the Lookup Table (LUT), Flip-Flop (FF), and power consumption decreased by 18.5%, 33.6%, and 26.6%, respectively, and converged 1.8 times as fast.

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Data Availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

This work was supported by the National Natural Science Foundation of China Youth Program (62105048), the Major Science and Technology Project of Chongqing Science and Technology Bureau (cstc2018jszx-cyztzxX0054), the Major Integrated Circuit Industry Project of Chongqing Science and Technology Commission (cstc2018jszx-cyztzx0217) and the Natural Science Foundation of Chongqing Science and Technology Bureau (CSTB2022NSCQ-MSX1389).

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Authors and Affiliations

  1. College of Optoelectronics Engineering, Chongqing University of Posts and Telecommunications, Chongqing, 400065, China

    Jun Yuan, Yuyang Zhang, Caizheng Yuan, Xiangsheng Meng & Yonghong Pan

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  1. Jun Yuan
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  2. Yuyang Zhang
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  3. Caizheng Yuan
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  4. Xiangsheng Meng
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Correspondence to Jun Yuan.

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Yuan, J., Zhang, Y., Yuan, C. et al. FPGA Design and Implementation of Improved DFxLMS Algorithm for Compressor Noise Cancellation System. Circuits Syst Signal Process 43, 2560–2584 (2024). https://doi.org/10.1007/s00034-023-02577-y

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