Design and Circuit Implementation of Area-Delay-Product-Efficient Logarithmic Converters Using Mantissa-Bit Compensation Scheme

Abstract

Autonomous cars, cloud computing and image recognition technology have spread drastically in recent years. However, operation of these applications requires a large number of multipliers and has a high hardware cost. Logarithmic converters can replace the multipliers at the expense of a large conversion error. This paper proposes a design for area-delay-product (ADP)-efficient logarithmic converters that use compensation methods involving mantissa bits. Replacing the conventional constant adder, bit-level manipulation and shift-and-add scheme, the proposed ADP-efficient logarithmic converters use mantissa bits to compensate for the conversion error of the accurate logarithmic curve. According to different specifications and applications of tolerable logarithmic conversion error, three sets of logarithmic converters, that is, methods 1, 2 and 3, were proposed to approximate the accurate logarithmic curve. The proposed ADP-efficient logarithmic converters can achieve a smaller implementation area, shorter latency and lower error than other methods in the literature. The total conversion errors of the proposed ADP-efficient logarithmic converters are 0.0379, 0.0303 and 0.0241 for methods 1, 2 and 3, respectively. Simultaneously, the proposed ADP-efficient logarithmic converters can attain ADP savings of 35.32, 69.71 and 66.19% compared to previous papers, for the proposed methods 1, 2 and 3. The design’s very-large-scale-integration (VLSI) hardware implementation is synthesized by the Taiwan Semiconductor Manufacture Company using 0.18 μm CMOS technology. Additionally, the proposed ADP-efficient implementation structure is ROM-free, fast, simple and has a lower logarithmic conversion error range. The proposed converters can be easily implemented by VLSI digital circuits and may be applied to 5G technology and digital signal processing.