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Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach

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Abstract

With the advancement in technology, various designs of multipliers offering low power consumption, high speed and less area have been proposed by many researchers. The main concern of electronic system designers is the energy minimization with the minimum penalty in speed and area for designing portable devices. Recent development focuses on the design of low-power multiplier for applications like biomedical signal processing requiring the least power consumption and delay-tolerant multiplier. This paper proposes a power-efficient design of the Wallace tree multiplier using a power-efficient 7:3 counter consisting of multiplexer and ex-or gates. The maximum power of the multiplier is consumed in the partial product tree reduction, and hence, in the proposed counter-based modular Wallace tree (CBMW) multiplier partial products are reduced using sequential 7:3 counter and the multi-bit addition in a single column reduces the complexity of the multiplier due to improvement in the locality. These proposed changes make design low power and scalable. The hardware utilization is minimum when a single 7:3 counter is used in partial product tree reduction per stage. The proposed multiplier is implemented in the Xilinx ISE design suite 14.7 using Verilog language on Spartan 3E FPGA. The design is also synthesized in Synopsys Design Compiler using 180 nm CMOS technology cell library. The corner analysis of the proposed design is performed in Synopsys PrimeTime, and the design meets all timing specifications. Also, the multiply and accumulate (MAC) unit is designed using the proposed multiplier to demonstrate an application of it. The detailed comparison is performed for 8-bit as well as 16-bit operands, and it shows that the CBMW multiplier gives better delay performance and consumes the least power compared to existing multipliers. It is proved to be an efficient multiplier in terms of Power-Delay Product (PDP). The power consumption of the proposed 16 \(\times \) 16 multiplier is 88.16 mW and 87.7 \(\mu \)W for Spartan 3E FPGA and ASIC design for 180 nm technology, respectively. It provides a promising performance for FPGA as well as for the ASIC platform.

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Data Availability Statement

The data that support the findings of this study are available from the corresponding author on request.

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Acknowledgements

This work was carried out under the support of the Special Manpower Development Program for Chips to System Design (SMDP-C2SD) project sponsored by Ministry of Electronics & Information Technology (MeitY), Government of India (New Delhi).

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  1. Electronics Engineering Department, Sardar Vallabhbhai National Institute of Technology, Surat, 395 007, India

    Vaibhavi Solanki, A. D. Darji & Harikrishna Singapuri

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  1. Vaibhavi Solanki
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Solanki, V., Darji, A.D. & Singapuri, H. Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach. Circuits Syst Signal Process 40, 4407–4427 (2021). https://doi.org/10.1007/s00034-021-01671-3

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