Abstract
This paper presents a fixed point design and implementation of a low-complexity high-throughput digital predistorter (DPD) on FPGA. Based on the memory polynomial model, a parallel structure is proposed for the implementation of the DPD and the effects of the fixed-point implementation on the performance are analyzed employing fidelity metrics such as modulation error ratio and adjacent channel power ratio. According to this analysis, an optimized fixed-point hardware implementation of the proposed DPD with proper word lengths is presented. Besides some simplifications to the proposed structure, a number of effective modifications are proposed for clock enhancement. The improved clock frequency of the proposed implementation makes it a fit choice for application over communication signals with considerable bandwidth. The required hardware and the maximum clock rate corresponding to these modifications are evaluated and reported. The performance of the proposed DPD in linearization of an actual power amplifier (PA) is also experimentally evaluated, through application of an appropriate hardware setup. Experimental results show about 11 dB ACPR improvement in the PA output for a 128-QAM test signal. The moderate hardware resource requirement of the proposed high-throughput DPD is also verified through comparison with some remarkable works in the same area.
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Notes
By the term “memory effect,” we refer to the dependence of the PA behavior (and thus its output) at a given point of time on the values of the input signal in the previous moments.
Critical path is defined as the path in the signal flow, over which signal experiences the most processing lag.
Allover this paper, SWL is assumed the same for input/output signals and all internal stages.
References
A.E. Abdelrahman, O. Hammi, A.K. Kwan, A. Zerguine, F.M. Ghannouchi, A novel weighted memory polynomial for behavioral modeling and digital predistortion of nonlinear wireless transmitters. IEEE Trans. Ind. Electron. 63(3), 1745–1753 (2016)
M. Amiri, S. Bassam, M. Helaoui, F.M. Ghannouchi, Estimation of crossover DPD using orthogonal polynomials in fixed point arithmetic. AEU Int. J. Electron. Commun. 67(11), 905–909 (2013)
A. Anastasijevic, D. Coja, N. Neskovic, A. Neskovic, D. Budimir, Joint power amplifier and I/Q modulator impairments modelling and compensation for LTE transmitters using artificial neural networks. AEU Int. J. Electron. Commun. 69(2), 529–538 (2015)
A.S. Ciminski, Neural network based adaptable control method for linearization of high power amplifiers. AEU Int. J. Electron. Commun. 59(4), 239–243 (2005)
S.C. Cripps, Advanced Techniques in RF Power Amplifier Design (Artech House, Norwood, 2002)
G. Cunha, S. Farsi, B. Nauwelaers, D. Schreurs, An FPGA-based digital predistorter for RF power amplifier linearization using cross-memory polynomial model, in 2014 International Workshop on Integrated Nonlinear Microwave and Millimetre-wave Circuits (INMMiC) (IEEE, 2014), pp. 1–3
J.L. Dawson, T.H. Lee, Cartesian feedback for RF power amplifier linearization, in: Proceedings of the 2004 American Control Conference, 2004, vol. 1 (IEEE, 2004), pp. 361–366
L. Ding, G.T. Zhou, D.R. Morgan, Z. Ma, J.S. Kenney, J. Kim, C.R. Giardina, A robust digital baseband predistorter constructed using memory polynomials. IEEE Trans. Commun. 52(1), 159–165 (2004)
M.M. Ebrahimi, S.A. Bassam, M. Helaoui, F.M. Ghannouchi, Applying memory polynomial model to linearize wideband multi-bit delta-sigma based transmitters. AEU Int. J. Electron. Commun. 66(8), 625–629 (2012)
K.M. Gharaibeh, A.S. Al-Zayed, Performance of feed-forward linearizers of power amplifiers in OFDM systems under complex gain errors. Int. J. Commun. Syst. 29(4), 734–747 (2016)
P.L. Gilabert, G. Montoro, E. Bertran, FPGA implementation of a real-time NARMA-based digital adaptive predistorter. IEEE Trans. Circuits Syst. II Express Briefs 58(7), 402–406 (2011)
L. Guan, A. Zhu, Low-cost FPGA implementation of Volterra series-based digital predistorter for RF power amplifiers. IEEE Trans. Microw. Theory Tech. 58(4), 866–872 (2010)
M. Helaoui, F.M. Ghannouchi, Linearization of power amplifiers using the reverse MM-LINC technique. IEEE Trans. Circuits Syst. II Express Briefs 57(1), 6–10 (2010)
P.B. Kenington, High Linearity RF Amplifier Design (Artech House, Inc., Norwood, 2000)
A. Kwan, F. Ghannouchi, O. Hammi, M. Helaoui, M. Smith, Look-up table-based digital predistorter implementation for field programmable gate arrays using long-term evolution signals with 60 MHz bandwidth. IET Sci. Meas. Technol. 6(3), 181–188 (2012)
H. Li, D.H. Kwon, D. Chen, Y. Chiu, A fast digital predistortion algorithm for radio-frequency power amplifier linearization with loop delay compensation. IEEE J. Sel. Top. Signal Process. 3(3), 374–383 (2009)
Y. Ma, Y. Yamao, Y. Akaiwa, C. Yu, FPGA implementation of adaptive digital predistorter with fast convergence rate and low complexity for multi-channel transmitters. IEEE Trans. Microw. Theory Tech. 61(11), 3961–3973 (2013)
V.J. Mathews, Adaptive polynomial filters. IEEE Signal Process. Mag. 8(3), 10–26 (1991). https://doi.org/10.1109/79.127998
G.J. Mazzaro, K.G. Gard, M.B. Steer, Linear amplification by time-multiplexed spectrum. IET Circuits Devices Syst. 4(5), 392–402 (2010)
M. Rawat, K. Rawat, F.M. Ghannouchi, Adaptive digital predistortion of wireless power amplifiers/transmitters using dynamic real-valued focused time-delay line neural networks. IEEE Trans. Microw. Theory Tech. 58(1), 95–104 (2010)
F. Taringou, O. Hammi, B. Srinivasan, R. Malhame, F.M. Ghannouchi, Behaviour modelling of wideband RF transmitters using Hammerstein–Wiener models. IET Circuits Devices Syst. 4(4), 282–290 (2010)
J. Wood, Behavioral Modeling and Linearization of RF Power Amplifiers (Artech House, Norwood, 2014)
G. Wunder et al., 5GNOW: non-orthogonal, asynchronous waveforms for future mobile applications. IEEE Commun. Mag. 52(2), 97–105 (2014)
G. Xu, T. Liu, Y. Ye, J. Li, F.M. Ghannouchi, Generalised two-box cascaded Hammerstein-like digital predistorter for wide-band RF power amplifiers. Electron. Lett. 52(4), 293–295 (2016)
S. Yao, H. Qian, K. Kang, M. Shen, A recursive least squares algorithm with reduced complexity for digital predistortion linearization, in 2013 IEEE International Conference on Acoustics, Speech and Signal Processing (2013), pp. 4736–4739. https://doi.org/10.1109/ICASSP.2013.6638559
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Rahmanian, S., Bateni, M.H. & Yazdian, E. Efficient FPGA Implementation of a Digital Predistorter for Power Amplifier Linearization. Circuits Syst Signal Process 39, 5618–5637 (2020). https://doi.org/10.1007/s00034-020-01423-9
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DOI: https://doi.org/10.1007/s00034-020-01423-9