Abstract
In this paper, a two-stage comparator with high voltage to time gain, low input-referred noise, offset with lesser delay is introduced. The effect of noise can be greatly reduced by increasing the gain of the comparator and reducing load at input MOS pair. The addition of NMOS as input from the first stage output reduces the load at the input pair and clock-enabled NMOS breaks the supply to ground path when the clock is disabled with clock-enabled PMOS for the reset phase increasing the transconductance of the second stage. For fair comparison, conventional and proposed comparators are designed in 90-nm CMOS technology with 1.2 V supply voltage. Simulated results show that the proposed comparator has an input-referred noise of 71.2 \({\upmu \text {V}/\sqrt{\text {Hz}}}\) with input-referred offset of 7.299 \(\text {mV}\) at \({V}_{cm}\) of 600 mV with a delay of 91 \(\text {pS}\) and gain of 94.63 \(\text {V}^2/\text {s}\) at 1 GHz clock frequency. The output is 30% faster than conventional comparators, this improvement suits the criteria for high-precision ADCs as the noise and offset are low at the designed frequency across all the corners.
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References
Siddharth RK, Satyanarayana YJ, Kumar YBN, Vasantha MH, Bonizzoni E (2020) A 1-V, 3-GHz strong-arm latch voltage comparator for high speed applications. IEEE Trans Circ Syst II Exp Briefs 67(12):2918–2922. https://doi.org/10.1109/TCSII.2020.2993064
Varshney V, Nagaria RK (2020) Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme. AEU Int J Electron Commun 116. Elsevier GmbH. https://doi.org/10.1016/j.aeue.2020.153068
Zhuang H, Tang H, Liu X (2020) Voltage comparator with 60% faster speed by using charge pump. IEEE Trans Circ Syst II Exp Briefs 67(12):2923–2927. https://doi.org/10.1109/TCSII.2020.2983928
Zhuang H, Cao W, Peng X, Tang H (2021) A three-stage comparator and its modified version with fast speed and low kickback. IEEE Trans Very Large Scale Integr (VLSI) Syst 29(7):1485–1489. https://doi.org/10.1109/TVLSI.2021.3077624
Bindra HS, Lokin CE, Schinkel D, Annema AJ, Nauta B (2018) A 1.2-V dynamic bias latch-type comparator in 65-Nm CMOS with 0.4-MV input noise. IEEE J Solid-State Circ 53(7):1902–12. Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/JSSC.2018.2820147
Khorami A, Sharifkhani M (2018) A low-power high-speed comparator for precise applications. IEEE Trans Very Large Scale Integr (VLSI) Syst 26(10):2038–2049. https://doi.org/10.1109/TVLSI.2018.2833037
Yeom S, Sim T, Han J (2023) An analysis of CMOS latched comparators. In: 2023 international conference on electronics, information, and communication (ICEIC), Singapore, pp 1–4. https://doi.org/10.1109/ICEIC57457.2023.10049873
Chevella S, O’Hare D, O’Connell I (2020) A low-power 1-V supply dynamic comparator. IEEE Solid-State Circ Lett 3:154–157. https://doi.org/10.1109/LSSC.2020.3009437
Rezapour A, Shamsi H, Abbasizadeh H, Lee KY (2018) Low power high speed dynamic comparator. In: Proceedings of IEEE international symposium on circuits and systems, May 2018. Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/ISCAS.2018.8351548
Sreya D, Kumar AS, Kalyani P (2022) Dynamic comparator design for high speed ADCs. In: 2022 first international conference on electrical, electronics, information and communication technologies (ICEEICT), Trichy, India, pp 1–5. https://doi.org/10.1109/ICEEICT53079.2022.9768408
Ramamurthy C, Parikh CD, Sen S (2021) Deterministic digital calibration technique for 1.5 bits/stage pipelined and algorithmic ADCs with finite Op-Amp gain and large capacitance mismatches. Circ Syst Sig Process 40(8):3684–3702. Birkhauser. https://doi.org/10.1007/s00034-021-01652-6
Maciel N, Marques EC, Naviner LAB, Cai H (2018) Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology. Microelectron Reliab 88–90:965–68. Elsevier Ltd. https://doi.org/10.1016/j.microrel.2018.07.114
Bandla K, Harikrishnan A, Pal D (2020) Design of low power, high speed, low offset and area efficient dynamic-latch comparator for SAR-ADC. In: Proceedings of 2020 international conference on innovative trends in communication and computer engineering, ITCE 2020. Institute of Electrical and Electronics Engineers Inc., pp 299–302. https://doi.org/10.1109/ITCE48509.2020.9047792
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Penubadi, A.K.R., Pasupathy, S. (2024). Design of Voltage Comparator with High Voltage to Time Gain for ADC Applications. In: Zen, H., Dasari, N.M., Latha, Y.M., Rao, S.S. (eds) Soft Computing and Signal Processing. ICSCSP 2023. Lecture Notes in Networks and Systems, vol 840. Springer, Singapore. https://doi.org/10.1007/978-981-99-8451-0_43
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