Abstract
The Residue Number System (RNS) is a non-weighted number system. Because of its inherent parallelism, it has been extensively studied and used in Digital Signal Processing (DSP) systems. A key arithmetic operation in residue-based real-time computing system is modulo multiplication. For small moduli, ROM-based structures are better at realizing multipliers. Implementations with arithmetic components are more for medium and large moduli due to the exponential growth of ROM sizes. The new modular multiplier introduced in this paper is capable of easily handling medium and large moduli. The multiplier unit is proposed in this paper using shift and add, followed by the modulo operation. The implementation results show that our proposed design outperforms existing architectures in terms of area and power consumption when using the TSMC-180 nm CMOS Technology. When compared to existing works, our proposed multiplier saves 86% to 93% of area and 65% to 83% of power. The proposed multiplier improves the existing DCT architecture by 18% in terms of area.
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This manuscript is the outcome of the research work carried out at National Institute of Technology Calicut and was supported by Ministry of Education, India.
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Kopperundevi, P., Prakash, M.S. (2024). Multiplier Design for the Modulo Set \(\left\{ {2^{n} - 1,2^{n} ,2^{n + 1} - 1} \right\}\) and Its Application in DCT for HEVC. In: Kalya, S., Kulkarni, M., Bhat, S. (eds) Advances in VLSI, Signal Processing, Power Electronics, IoT, Communication and Embedded Systems. VSPICE 2022. Lecture Notes in Electrical Engineering, vol 1062. Springer, Singapore. https://doi.org/10.1007/978-981-99-4444-6_3
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DOI: https://doi.org/10.1007/978-981-99-4444-6_3
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