Abstract
Network on Chip (NoC) is very useful in connecting the different components of a chip. Many NoC topologies like 2D mesh, torus etc. are already in use. RiCoBiT (Ring Connected Binary Tree) is a new topology which was recently proposed and studied. RiCoBiT is a topology where performance parameters like maximum hop and average hop are better than the other topologies. Area parameters like wirelength and number of wire segments are approximately the same as compared to other topologies, but one of the biggest problems with this topology was the lack of an adaptive routing algorithm. Thus, we propose a new routing algorithm which is adaptive in nature. The algorithm is tested for all cases: destination and source in the same ring, destination is above the source ring, and the destination is below the source ring. The testing of the algorithm was performed by using a simulation setup for E-RiCoBiT- II (Enhanced RiCoBiT). It is observed that the topology is 100. The average hop, maximum hop, and total time are studied for the proposed architecture and algorithm.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
William J Dally (2001) Brian towles, route packets not wires : on chip interconnection network, DAC 2001
Tobias Bjerregaard, Shankar Mahadevan (2006) A survey of research and practices of network on chip, ACM Computing Survey
Sanju V, Niranjan Chiplunkar (2016) RiCoBiT—Ring connected binary tree : a structured and scalable architecture for network on chip based systems : An exclusive summary. In: International Conference on Data Engineering and Communication Technology-ICDECT, Pune, March 10– 11
Ville Rantala, Teijo Lehtonen, Juha Plosila (2006) Network on chip routing algorithms, TUCS Technical Report No 779
Sanju V, Koushika C, Sharmili R.Niranjan Chiplunkar, Khalid M, (2014) Design and implementation of a network on chip based simulator – a performance study In: International Journal of Computational Science and Engineering, Inderscience Publishers. 9(1/2) Pg No 95–105
Sanju V, Suresh Mandia, Nancy Jain, Nikita Jaiswal, Niranjan Chiplunkar, Khalid M (2015) Design and implementation of RiCoBiT: A structured and Scalable Architecture for network on chip based systems. In: International Journal of Computing and Digital Systems, 4(1), Pg No 63 – 71
Ahmed Hemani, Axel Jantsch, Shashi Kumar, Adam Postula, Johnny O¨ berg, Mikael Millberg, Dan Lindqvist (2001) Network on a chip: an architecture for billion transistor Era, DAC
Nurmi J (2005) Network-on-Chip: a new paradigm for system-on-chip design. In: Proceedings 2005 International Symposium on System-on-Chip, 15– 17
Israel Cidon, Idit Keidar (2006) Zooming in on Network on Chip Architec- tures, Intel Technical Magazine
Kumar S, Jantsch A, Soininen J, Forsell M, Millberg M, Oberg J, Tiensyrja K, Hemani A (2002) A network on chip architecture and design methodology In: Proceedings International Symposium VLSI (ISVLSI), pp 117–124
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2024 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Sanju, V., Manvi, S.K., Shah, J.A., Taqhi, H., Mishra, H., Chetana Reddy, P. (2024). E—RiCoBiT—II: A High Performing RiCoBiT (Ring Connected Binary Tree) Topology with Fully Adaptive Routing Algorithm. In: Kalya, S., Kulkarni, M., Bhat, S. (eds) Advances in VLSI, Signal Processing, Power Electronics, IoT, Communication and Embedded Systems. VSPICE 2022. Lecture Notes in Electrical Engineering, vol 1062. Springer, Singapore. https://doi.org/10.1007/978-981-99-4444-6_21
Download citation
DOI: https://doi.org/10.1007/978-981-99-4444-6_21
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-99-4443-9
Online ISBN: 978-981-99-4444-6
eBook Packages: EngineeringEngineering (R0)