Efficient FPGA-Based Implementation of Image Segmentation Algorithms for IoT Applications

Abstract

The technique of segmenting a picture involves breaking it up into its component parts, such as boundaries and regions. Image edges are found via Edge detection algorithms. Edges of the picture are detected when the pixels’ intensities abruptly shift. Sobel, Prewitt, and Robert are three well-known gradient-based edge detection algorithms that operate on the 3-by-3 and 2-by-2 kernels in the X and Y axis. Python and Verilog HDL for synthesis on the Artix 7-based Basys 3 dev kit are used to perform in two separate phases. The image data is first converted to grayscale for the Python implementation before being passed through the gradient-based edge detection (Sobel, Prewitt, and Robert) operator. The edges of the entire image are then determined using an edge detection technique. The resultant picture is then examined using various input parameters including PSNR, MSE. The input grayscale image is passed via line buffers, which store the pixels for subsequent processing by the operators, in the second stage, which is Verilog implementation. Output buffer is then filled based on the output from the convolution operator. The kernels of 3 × 3 or 2 × 2 for the convolution are pre-defined based on the operator.