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A Novel Approach for Reversible Realization of 4 × 4 Bit Vedic Multiplier Circuit

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Advances in VLSI, Communication, and Signal Processing

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 587))

Abstract

The availability of fast and efficient processing systems is the basic requirement of current era. In digital systems, multiplications is one of the major operations, which limit the speed and efficiency of the system. This paper describes a novel approach for the Reversible realization of 4-Bit Vedic multiplier circuit with optimized performance parameters. Vedic multipliers are based on the concept of Vedic mathematics. It is a very fast multiplier, as it generates all the partial products and their sum in single step only. Moreover, designing of this multiplier using reversible approach will lead to the low loss fast multiplier circuits for digital systems. Some parameters indicating performance of the circuit, such as number of gates (TG), constant inputs (CI), garbage outputs (GO) and quantum cost (QC) of proposed multiplier design is also compared and analyzed with the earlier designs.

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Authors and Affiliations

  1. Amity University Uttar Pradesh, Lucknow Campus, Lucknow, India

    Vandana Shukla, O. P. Singh & G. R. Mishra

  2. Dr. Ram Manohar Lohia Avadh University, Faizabad, India

    R. K. Tiwari

Authors
  1. Vandana Shukla
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  2. O. P. Singh
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  3. G. R. Mishra
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  4. R. K. Tiwari
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Corresponding author

Correspondence to Vandana Shukla .

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Editors and Affiliations

  1. Ministry of Electronics and Information Technology, New Delhi, Delhi, India

    Debashis Dutta

  2. Motilal Nehru National Institute of Technology Allahabad, Allahabad, Uttar Pradesh, India

    Haranath Kar

  3. Indian Institute of Technology (ISM), Dhanbad, Jharkhand, India

    Chiranjeev Kumar

  4. Motilal Nehru National Institute of Technology Allahabad, Allahabad, Uttar Pradesh, India

    Vijaya Bhadauria

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Shukla, V., Singh, O.P., Mishra, G.R., Tiwari, R.K. (2020). A Novel Approach for Reversible Realization of 4 × 4 Bit Vedic Multiplier Circuit. In: Dutta, D., Kar, H., Kumar, C., Bhadauria, V. (eds) Advances in VLSI, Communication, and Signal Processing. Lecture Notes in Electrical Engineering, vol 587. Springer, Singapore. https://doi.org/10.1007/978-981-32-9775-3_67

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  • DOI: https://doi.org/10.1007/978-981-32-9775-3_67

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-32-9774-6

  • Online ISBN: 978-981-32-9775-3

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