Abstract
An efficient FPGA or ASIC based hardware implementation of deep neural networks face the challenge of limited chip area, and therefore an area efficient architecture is required to fully harness the capacity of parallel processing of FPGA and ASIC in contrast to general purpose processors. In literature, the challenges are to investigate a generalized mathematical model and architecture for neuron block in an ANN implementation. We have proposed a generalized architecture for neuron implementation based on the shift-and-add algorithm, collectively known as Coordinate Rotation Digital Computer (CORDIC) algorithm, having a wide range of application. The look-up-table (LUT) based approach with a shift-and-add algorithm is an alternative technique for polynomial approximation and implementation. Paper explains how the CORDIC algorithm works and investigates the power and area efficient versatile computational unit for ANN application. The derived model proves that for the hyperbolic tangent function required a double pseudo-rotation and additional subtraction compares to the sigmoid function. In this reference versatile approach based optimized sigmoid activation function is implemented. The function is synthesized and validate on Xilinx zynq XC7Z010clg400 SoC and result reveals the minimum resources utilization.
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Acknowledgment
The authors would like to thank the University Grant Commission (UGC) New Delhi, Government of India under JRF scheme with award no. 22745/(NET-DEC. 2015) for providing financial support and Special Manpower Development Program Chip to System Design, Department of Electronics and Information Technology (DeitY) under the Ministry of Electronics and Information Technology, Government of India for providing necessary Research Facilities.
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Raut, G., Bhartiy, V., Rajput, G., Khan, S., Beohar, A., Vishvakarma, S.K. (2019). Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_28
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