Analysis of the Efficiency of Parallel Prefix Adders

Abstract

ALU is at the core of each and every processing unit, as well as the adder circuit would be at the core of any ALU. The adder performs subtraction and is the fundamental component of multipliers’ circuitry. Due to the fact that additions are the most basic arithmetic function and adder has become the most essential arithmetic part of the processing unit, the topic of VLSI arithmetic must have captivated numerous modern VLSI researchers over the decades. Numerous conventional and creative ways have been developed over the years to maximize the efficiency of the addition in latency, energy consumption, and area. This article reviews a few classical addition methods, evaluates their efficiency, and afterwards assesses and analyses the performance of different parallel prefix adders. These prefix adders have become currently the most effective method for DSP processors. The objective is to choose the optimal adder from among those presented for a specific application in terms of on-chip power usage, resource use, and computation speed. The adders have been designed in Verilog HDL using Vivado Design Suite on Xilinx ZYNQ-7000 series SoCs.