Abstract
Time-to-digital converters are utilized to represent time in digital format whenever the time pulse is given as an input. The vital requirements for mainstream applications include a broad measurement range, low cost, high resolution, voltage sensitivity, and temperature sensitivity. Previously, many TDCs have been designed using application specific integrated circuits (ASICs), in order to attain resolution more than 10 ps. But, implementation using ASIC does not provide reprogramming feature. Therefore, this paper proposes the new concept of time-to-digital converter (TDC) using FPGA with high resolution. In this concept, the given input signals are sampled n number of times. The timing reference is obtained by feeding the original clock signal to tapped delay lines. A single reference time period is obtained in accordance with the periodicity for achieving high resolution. Finally, this high resolution TDC is implemented in the VERILOG and synthesized using XILINX FPGA. The performance of TDC is also evaluated in terms of power, delay, and area, and a high resolution of 10 ps has been achieved.
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Acknowledgements
The authors would like to acknowledge the Management, Principal, and Head of the Department of Electronics and Communication Engineering of Sri Ramakrishna Engineering College, Coimbatore for the facilities provided for the successful completion of the project.
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Mangalam, H., Meishree, S., Mageshwari, S., Prathiksha, B. (2023). FPGA-Based Implementation of Time-To-Digital Converter. In: Smys, S., Kamel, K.A., Palanisamy, R. (eds) Inventive Computation and Information Technologies. Lecture Notes in Networks and Systems, vol 563. Springer, Singapore. https://doi.org/10.1007/978-981-19-7402-1_47
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DOI: https://doi.org/10.1007/978-981-19-7402-1_47
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