Abstract
Encryption is the primary way for ensuring communication security. The symmetric key method, often known as Advanced Encryption Standard (AES), is a well-known technique in the field of security. AES can be implemented in either software or hardware. In the current study, Field Programmable Gate Arrays (FPGAs) are utilized to implement AES. Number of studies have been done on experiments of AES using FPGAs. Till date, no study has been done on the architectures that are being utilized to implement AES on FPGA. This paper provides an in-depth examination of several hardware implementation of AES on FPGA in terms of through put and performance. This survey article enables the engineers to choose the best architecture of FPGAs to implement AES algorithm in terms of design as per the requirement. The surveyed architectures are sequential, pipelined, iterative, and parallel. Parallel architectures with pipelining between rounds have shown an excellent throughput. Certain improved S-box and key expansion approaches have also been employed by the researchers to reduce the hardware areas.
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Hasija, T., Kaur, A., Ramkumar, K.R., Sharma, S., Mittal, S., Singh, B. (2023). A Survey on Performance Analysis of Different Architectures of AES Algorithm on FPGA. In: Agrawal, R., Kishore Singh, C., Goyal, A., Singh, D.K. (eds) Modern Electronics Devices and Communication Systems. Lecture Notes in Electrical Engineering, vol 948. Springer, Singapore. https://doi.org/10.1007/978-981-19-6383-4_4
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