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Slew-Rate Enhancement of a Full-On Chip CMOS LDO Based on a Capacitorless Push–Pull Current Booster Circuit

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Proceedings of the 3rd International Conference on Electronic Engineering and Renewable Energy Systems (ICEERE 2022)

Abstract

In this paper, a full-on chip low drop-Out voltage regulator (LDO) with a simple Slew-Rate Enhancement Circuit (SREC) has been proposed and simulated in TSMC 0.18 μm CMOS process. The proposed SREC technique has been  designed mainly to improve the transient response at full load by using only active components to minimize the space area of the chip as low as possible. The proposed LDO presents a quiescent current (IQ) of 14 μA at input voltage (Vint) of 1.8 V, providing a 60 mA load current (Iload) with 1.6 V output voltage (Vout) and drop-out voltage (VDO) of 200 mV. The simulation results show the system stability under different load conditions. The load regulation has been improved with a nominal output voltage recovery time less than 900 ns and the output over/undershoot values are 156 mV and 190 mV, respectively.

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Correspondence to Kamal Zared .

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Zared, K., Ameziane, H., Alami Hassani, A., Akhamal, H., Jamil Ouazzani, M., Qjidaa, H. (2023). Slew-Rate Enhancement of a Full-On Chip CMOS LDO Based on a Capacitorless Push–Pull Current Booster Circuit. In: Bekkay, H., Mellit, A., Gagliano, A., Rabhi, A., Amine Koulali, M. (eds) Proceedings of the 3rd International Conference on Electronic Engineering and Renewable Energy Systems. ICEERE 2022. Lecture Notes in Electrical Engineering, vol 954. Springer, Singapore. https://doi.org/10.1007/978-981-19-6223-3_37

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  • DOI: https://doi.org/10.1007/978-981-19-6223-3_37

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-19-6222-6

  • Online ISBN: 978-981-19-6223-3

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