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Performance Enhancement of SiGe-Based Junctionless Tri-Gate (JL-TG) FinFETs Using Hetero-High-K Gate Oxide Material

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Advances in VLSI, Communication, and Signal Processing

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 911))

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Abstract

This paper endeavors to utilize the combined advantages of Hetero-High-K gate stack material on SiGe fin with Junctionless triple gate structure and proposes three devices with different oxide materials and placement. The potential distribution, electrostatic, analog, and RF parameters of the proposed devices are analyzed and compared. Crucial FOMs like on/off current ratio, DIBL, Transconductance, Early voltage, cut-off frequency, GFP, TFP, GTFP, etc., are discussed.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Kanpur Institute of Technology, Kanpur, Uttar Pradesh, India

    Himanshi Awasthi

  2. Department of Electronics Engineering, Rajkiya Engineering College Sonbhadra, Sonbhadra, Uttar Pradesh, India

    Deepak Sigroha & Abhinav Gupta

  3. Department of Electronics and Communication Engineering, Meerut Institute of Engineering and Technology, Meerut, Uttar Pradesh, India

    Vikrant Varshney

  4. Department of Electronics and Communication Engineering, M.N.N.I.T. Allahabad, Prayagraj, Uttar Pradesh, India

    Manish Kumar Rai & Sanjeev Rai

Authors
  1. Himanshi Awasthi
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  2. Deepak Sigroha
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  3. Vikrant Varshney
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  4. Manish Kumar Rai
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  5. Sanjeev Rai
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  6. Abhinav Gupta
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Corresponding author

Correspondence to Abhinav Gupta .

Editor information

Editors and Affiliations

  1. Electronics and Communication, Motilal Nehru National Institute of Technology, Allahabad, India

    Amit Dhawan

  2. Electronics and Communication, Motilal Nehru National Institute of Technology, Allahabad, India

    R. A. Mishra

  3. Information and Communication Technology, ABV-Indian Institute of Information Technology and Management, Gwalior, India

    Karm Veer Arya

  4. Department of EEC Engineering, Universidad Publica de Navarra, Pamplona, Spain

    Carlos Ruiz Zamarreño

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Awasthi, H., Sigroha, D., Varshney, V., Rai, M.K., Rai, S., Gupta, A. (2022). Performance Enhancement of SiGe-Based Junctionless Tri-Gate (JL-TG) FinFETs Using Hetero-High-K Gate Oxide Material. In: Dhawan, A., Mishra, R.A., Arya, K.V., Zamarreño, C.R. (eds) Advances in VLSI, Communication, and Signal Processing. Lecture Notes in Electrical Engineering, vol 911. Springer, Singapore. https://doi.org/10.1007/978-981-19-2631-0_47

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  • DOI: https://doi.org/10.1007/978-981-19-2631-0_47

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-19-2630-3

  • Online ISBN: 978-981-19-2631-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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