Abstract
In the current semiconductor era, MOSFET gradually losses its performance to the short channel effect (SCE) due to decreasing channel length. Advanced FinFET technology introduces reduction in the SCEs. A tri-gate FinFET, where the range of the gate is 14 nm, is accomplished and presented here using Silvaco TCAD. The geometrical dimensions of the device are characterized based on the width and the height of the fin to attain an aspect ratio of 0.5, 1, and 2. It can be reformed in two ways where firstly width is constant with varying heights to get aspect ratio and vice versa. The electrical parameters such as Ion current, threshold voltage, sub threshold current, drain-induced barrier lowering, and Ion/Ioff current ratio are compared for the different aspect ratios to attain an optimized aspect ratio and also from the ID–VGS graph, the threshold voltage is determined with respect to VDS. The logarithmic ID–VGS graph depicts the leakage current. Thereby, the development of the TG FinFET structure is proposed, where the standardized schematic is at fixed height, width, and length of 10 nm.
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Acknowledgements
The authors are indebted to Dept. of Electronics and Communication Engineering, National Institute of Technology Mizoram for providing flexible platform, facilities and support to grow skill for carry out this work.
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Saha, P., Nanda, S., Yugender, P., Dhar, R.S. (2023). Effects of Dimensional Variations on Short Channel Parameters in 14 nm Channel Length TG–SOI FinFETs. In: Dhar, S., Do, DT., Sur, S.N., Liu, H.CM. (eds) Advances in Communication, Devices and Networking. Lecture Notes in Electrical Engineering, vol 902. Springer, Singapore. https://doi.org/10.1007/978-981-19-2004-2_4
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DOI: https://doi.org/10.1007/978-981-19-2004-2_4
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