Abstract
In spite of momentous attention received by the higher-radix signed-digit number systems, no significant work on the related reverse conversion has been reported yet. In this paper, it is shown that some minor pre-processing of higher-radix inputs may allow constituting the conversion control network for reverse conversion of higher-radix signed-digit number systems merely in terms of binary signed-digit number system. Subsequently several alternatives may become available for exploiting the reduced logical design at ease, considering various block factors at different levels of the conversion control network. As a case study, the 16-digit minimally redundant radix-4 signed-digit number system is investigated in this paper and on the basis of simulative study, the most potential candidate is determined for designing the convertor.
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Chakraborty, M.S., Sreelakshmi, G., Chakraborty, A., Sao, S.K., Sahana, D.C. (2022). Towards Area-Delay Efficient Reverse Conversion of Higher-Radix Signed-Digit Number Systems. In: Sengodan, T., Murugappan, M., Misra, S. (eds) Advances in Electrical and Computer Technologies. ICAECT 2021. Lecture Notes in Electrical Engineering, vol 881. Springer, Singapore. https://doi.org/10.1007/978-981-19-1111-8_1
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