Abstract
Quantum-dot cellular automata (QCA) is an inventive nano-level computation which suggests less dimension and less power consumption, with more speed and premeditated as an amplification to the scaling obstacle with CMOS methodology. One of the newest and rising nanotechnologies used today is QCA based on the repulsion of Coulomb. The enhancement of RAM is expanding with each passing day. This can be primarily due to the advancement of handheld, portable devices such as smart phones and laptops. Cache memory is utilized within the microprocessor to get data quicker. In this paper, cell optimization and realization of the QCA XOR gate are suggested, and further this QCA XOR gate is used to design 2:1 QCA MUX and these QCA structures will be utilized to design interesting and ideal designs of QCA RAM. The proposed QCA RAM contains less number of cells and lesser cost as related to its best previous QCA layouts. The comprehensive analysis of the proposed design suggests that the proposed RAM cell architecture is 61.53% cost efficient and 68.18% area decrement as compared to its best previous existing layout. The suggested circuits are executed and tested with the QCA designer simulation environment. The simulation outcomes illustrate that the suggested architecture outperforms in comparison with best counterpart designs in terms of quantum cell count, area and latency.
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Tripathi, D., Wairya, S. (2023). A Cost-Efficient QCA RAM Cell for Nanotechnology Applications. In: Mishra, B., Tiwari, M. (eds) VLSI, Microwave and Wireless Technologies. Lecture Notes in Electrical Engineering, vol 877. Springer, Singapore. https://doi.org/10.1007/978-981-19-0312-0_14
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DOI: https://doi.org/10.1007/978-981-19-0312-0_14
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