Abstract
RISC-V is a free and open instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. RISC-V ISA enables a new phase in the field of processors through open standard association. The address of RISC-V is based on 32-bit and 64-bit variants. The essential RISC-V is a 32-bit integer instruction set defined as RV32I, which efficiently supports the operating system environments and also suits for the embedded system applications. In this paper, a survey is carried for 5-stage in-order pipeline implementation and ways to overcome pipelining hazards for structural hazards, data hazards, and control hazards on RISC-V processors. Being open-source and free, this is adopted in many commercial and academic research and projects.
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Mallidu, J., Siddamal, S.V. (2023). A Survey on In-Order 5-Stage Pipeline RISC-V Processor Implementation. In: Kaiser, M.S., Xie, J., Rathore, V.S. (eds) Information and Communication Technology for Competitive Strategies (ICTCS 2021). Lecture Notes in Networks and Systems, vol 401. Springer, Singapore. https://doi.org/10.1007/978-981-19-0098-3_73
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DOI: https://doi.org/10.1007/978-981-19-0098-3_73
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