Machine Learning Based and Reconfigurable Architecture with a Countermeasure for Side Channel Attacks

Abstract

Cryptographic devices, which are embedded in SoC systems and mathematically secured algorithms, are used for operating it. But a side channel leakage may cause the secret data in these systems to be at high risk. Particularly, cryptography circuits like ECC algorithm are prone to power attacks like correlation power analysis (CPA) and differential power analysis (DPA). Hence, it is necessary to safeguard the sensitive information using proposed method having ECC with countermeasure. This paper focuses on protecting sensitive information using chaotic countermeasure as reconfigurable architecture by adopting ARTIX-7 board and offline ELM algorithm to detect the attack. In this, an effective countermeasure is designed and implemented using the FPGA for attack detection. Moreover, the proposed chaotic architecture has been integrated with ECC bit key mounted on ARTIX-7 board and tested nearly with 250 power traces recorded from the architecture. We have compared the proposed chaotic maps with the other current countermeasure technique, such as WDDL, IVR, and inductive ECC, in which the proposed design outperforms the above described existing structures in terms of area usage, power overhead, and frequency overhead. And to verify the strength of the encryption algorithm by using NIST to ensure that the given random number can be used for cryptographic purposes.