Radix-10 Multiplier Implementation with Carry Skip Adder Using Verilog

Abstract

Multiplier plays a vital role in different applications hence more number of multiplier applications are available, as there is a high requirement of multipliers in the various applications, it is required to develop a high speed and area efficient multiplier. This article explains the design and development of high speed and area efficient multiplier using Verilog. In this work, a new 16 bit multiplication unit has been designed and implemented. The proposed multiplier will incorporate for developing the multiplier and it will be using a binary coded decimal adder and carry skip adder, and CSKA has a higher speed and lower energy consumption. For calculating multiples of multiplicand BCD Adder will be used and for calculating sum of partial products CSKA Adder will be used. Parallel path is used for carry propagation in the carry skip adder. Hence, time taken for propagation delay can be reduced in the adder. 16-bit Multipliers is designed, implemented and explained in this paper. The important factors need to improve for designing multiplier is less area, high speed and low power.