Abstract
Digital filters are primary and important part in digital signal processing, often used in the scope of separation or restoration of signals. Due to inherent properties and advantages of finite impulse response (FIR) filter, it is more preferred over infinite impulse response (IIR) filter. In the present work, bottlenecks of various FIR filter architecture are discussed to estimate and understand the impact of these architectures on reconfigurable platform. The RTL implementation of various architectures is focused while justifying the critical path and the computation complexity involved. Use of symmetric coefficients (SC) is a key in reducing the area constrains of filter, and further use of data representation for coefficient is addressed with CSD and its impact is discussed. Impact of pipeline and parallel architectures is discussed, and their performance is evaluated for reconfigurable platform.
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We would like to thank Head of Research Center, Department of E&CE, SDMCET, Dharwad for proving us the tools, resources and platform to carry out the research.
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Shinde, K.D., Vijaya, C. (2022). Bottlenecks in Finite Impulse Response Filter Architectures on a Reconfigurable Platform. In: Shetty D., P., Shetty, S. (eds) Recent Advances in Artificial Intelligence and Data Engineering. Advances in Intelligent Systems and Computing, vol 1386. Springer, Singapore. https://doi.org/10.1007/978-981-16-3342-3_26
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DOI: https://doi.org/10.1007/978-981-16-3342-3_26
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