Abstract
Floorplanning is the first step in the physical design of VLSI. At this stage, the circuit is partitioned into blocks for packing them optimally within the chip. The metrics minimized in floorplan are overall interconnect wirelength, area of the chip, deadspace, etc. B* tree is a popular representation of floorplan as it captures both slicing and non-slicing floorplans. In this work, we have proposed a greedy algorithm for the initial floorplan, which can be used by simulated annealing placer that takes B* tree as the initial floorplan. The proposed algorithm in conjunction with B* tree when integrated into simulated annealing placer and experimented on MCNC benchmarks reduces the overall wirelength on an average by 11% and 69% as compared to random and prior greedy initial floorplans.
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Ray, B.N.B., Sahoo, S.S., Mohanty, S.K. (2021). G-NSVF: A Greedy Algorithm for Non-Slicing VLSI Floorplanning. In: Behera, P.K., Sethi, P.C. (eds) Digital Democracy – IT for Change. CSI 2020. Communications in Computer and Information Science, vol 1372. Springer, Singapore. https://doi.org/10.1007/978-981-16-2723-1_6
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DOI: https://doi.org/10.1007/978-981-16-2723-1_6
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