High-Performance Encoded-Driven LFSR for Improved Fault Coverage

Abstract

Due to the emergence of new digital transformation and recent advancements in nanotechnology, testing becomes a difficult task to accomplish in many circuits. There are several numerous investigations done by many researchers well prove that Linear Feedback Shift Register (LFSR) is the predominant test pattern generator for BIST. However, it requires some unique modifications for reduced power consumption and improved fault coverage and each causes some significant performance tradeoffs. The proposed TPG uses encoder-driven Linear Feedback Shift Register (BS-LFSR) architecture, which replaced dynamic polynomial computation and periodic reseeding mechanism with some decomposition and concatenation techniques to overcome the limitations while retaining the inherent characteristics. This paper considers the complexity and energy-related issues in LFSR-based BIST implementation without compromising the fault coverage and tends to narrow down the complexity and energy overhead for improved system performance. The objective of this paper is twofold. One, to prove the effectiveness of proposed encoded-driven LFSR over existing multi-polynomial and reseeding LFSR. It is shown that the proposed LFSR-TPG consumes lesser hardware and outperforms other LFSR models in terms of operating speed. Second, to carry out experimental evaluation over ISCAS85 and 89 benchmark datasets and to validate the fault coverage and energy efficiency measures.