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A Memory-Efficient Adaptive Optimal Binary Search Tree Architecture for IPV6 Lookup Address

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Mobile Computing and Sustainable Informatics

Abstract

The Internet protocol version 6 which has an increase in address length with prefix length poses challenges in memory efficiency, incremental updates. So this work proposes adaptive optimal binary search tree (AOBT) based IPv6 lookup (AOBT-IL) architecture. An adaptive optimal binary search tree (AOBT) structure is introduced for the minimization of memory utilization. An Altera Quartus Stratix II device with Verilog HDL implements the IP lookup design. The proposed method performance is validated using different lookup table sizes with comparative analysis. The proposed method accomplished better outcomes in the case of maximum frequency, memory, SRAM, and logic elements results when compared to existing methods such as balanced parallelized frugal lookup (BPFL), linear pipelined IPv6 lookup architecture (IPILA) and parallel optimized linear pipeline (POLP) methods.

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References

  1. J. Iurman, B. Donnet, F. Brockners,Implementation of IPV6 IOAM in Linux Kernel, in Proceedings of Technical Conference on Linux Networking (Netdev 0x14) (2020)

    Google Scholar 

  2. O. Erdem, A. Carus, H. Le, Value-coded trie structure for high-performance IPv6 lookup. Comput. J. 58(2), 204–214 (2015)

    Article  Google Scholar 

  3. Y.K. Li, D. Pao, Address lookup algorithms for IPv6. IEE Proc. Commun. 153(6), 909–918 (2006)

    Article  Google Scholar 

  4. Y. Qu, V.K. Prasanna, High-performance pipelined architecture for tree-based IP lookup engine on FPGA, in 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Ph.D. Forum (IEEE, May 2013), pp. 114–123

    Google Scholar 

  5. H. Le, V.K. Prasanna, Scalable tree-based architectures for IPv4/v6 lookup using prefix partitioning. IEEE Trans. Comput. 61(7), 1026–1039 (2011)

    Article  MathSciNet  Google Scholar 

  6. J. Li, Z. Sun, J. Yan, X. Yang, Y. Jiang, W. Quan, DrawerPipe: a reconfigurable pipeline for network processing on FPGA-based SmartNIC. Electronics 9(1), 59 (2020)

    Article  Google Scholar 

  7. A. Yazdinejad, R.M. Parizi, A. Bohlooli, A. Dehghantanha, K.-K.R. Choo, A high-performance framework for a network programmable packet processor using P4 and FPGA. J. Netw. Comput. Appl. 156, 102564 (2020)

    Google Scholar 

  8. F. Lin, G. Wang, J. Zhou, S. Zhang, X. Yao, High-performance IPv6 address lookup in GPU-accelerated software routers. J. Netw. Comput. Appl. 74, 1–10 (2016)

    Article  Google Scholar 

  9. I. Simsek, Blind packet forwarding in a hierarchical level-based locator/identifier split. Comput. Commun. 150, 286–303 (2020)

    Article  Google Scholar 

  10. M. Kekely, L. Kekely, J. Kořenek, General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocess. Microsyst. 73, 102950 (2020)

    Article  Google Scholar 

  11. Z. Chicha, L. Milinkovic, A. Smiljanic, FPGA implementation of lookup algorithms, in 2011 IEEE 12th International Conference on High Performance Switching and Routing (IEEE, 2011), pp. 270–275

    Google Scholar 

  12. Y.K. Chang, Y.C. Lin, C.C. Su, Dynamic multiway segment tree for IP lookups and the fast pipelined search engine. IEEE Trans. Comput. 59(4), 492–506 (2009)

    Article  MathSciNet  Google Scholar 

  13. D. Pao, Lu. Ziyan, A multi-pipeline architecture for high-speed packet classification. Comput. Commun. 54, 84–96 (2014)

    Article  Google Scholar 

  14. D. Xin, J. Han, K.C. Chang, Progressive and selective merge: computing top-k with ad-hoc ranking functions, in Proceedings of the 2007 ACM SIGMOD International Conference on Management of Data, June 2007, pp. 103–114

    Google Scholar 

  15. J.C. Vega, M.A. Merlini, P. Chow, FFShark: a 100G FPGA implementation of BPF filtering for Wireshark, in 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (IEEE, 2020), pp. 47–55

    Google Scholar 

  16. T. Stimpfling, N. Bélanger, J.P. Langlois, Y. Savaria, SHIP: a scalable high-performance IPv6 lookup algorithm that exploits prefix characteristics. IEEE/ACM Trans. Netw. 27(4), 1529–1542 (2019)

    Article  Google Scholar 

  17. R.K. Sevakula, N.K. Verma, Balanced binary search tree multiclass decomposition method with possible non-outliers. SN Appl. Sci. 2, 1–15 (2020)

    Article  Google Scholar 

  18. C. Luo, Internet enterprise organization strategy based on FPGA and machine learning. Microprocess. Microsyst. 103714 (2020)

    Google Scholar 

  19. C. Huang, Modern art network communication based on FPGA and convolutional neural network. Microprocess. Microsyst. 103498 (2020)

    Google Scholar 

  20. P. Alapati, V.K. Tavva, M. Mutyam, A scalable and energy-efficient concurrent binary search tree with fatnodes. IEEE Trans. Sustain. Comput. 5(4), 468–484 (2020)

    Article  Google Scholar 

  21. T. Beneš, M. Kekely, K. Hynek, T. Čejka, Pipelined ALU for effective external memory access in FPGA, in 2020 23rd Euromicro Conference on Digital System Design (DSD) (IEEE, 2020), pp. 97–100

    Google Scholar 

  22. A. Kushwaha, S. Sharma, N. Bazard, A. Gumaste, B. Mukherjee, Design, analysis, and a terabit implementation of a source-routing-based SDN data plane. IEEE Syst. J. (2020)

    Google Scholar 

  23. L. Kekely, J. Cabal, V. Puš, J. Kořenek, Multi buses: theory and practical considerations of data bus width scaling in FPGAs, in 2020 23rd Euromicro Conference on Digital System Design (DSD) (IEEE, 2020), pp. 49–56

    Google Scholar 

  24. Y. Hu, G. Cheng, Y. Tang, F. Wang, A practical design of hash functions for IPv6 using multi-objective genetic programming. Comput. Commun. 162, 160–168 (2020)

    Article  Google Scholar 

  25. M.M. Vijay, D. Shalini Punithavathani, Implementation of memory-efficient linear pipelined IPv6 lookup and its significance in smart cities. Comput. Electr. Eng. 67, 1–14 (2018)

    Google Scholar 

  26. D. Pao, Z. Lu, A multi-pipeline architecture for high-speed packet classification. Comput. Commun. 54, 84–96 (2014)

    Article  Google Scholar 

  27. J.J. Kester, Comparing the accuracy of IPv4 and IPv6 geolocation databases. Methodology 10(11), 12–17 (2016)

    Google Scholar 

  28. M. Hemalatha, S. Rukmanidevi, N.R. Shanker, Searching time operation reduced IPV6 matching through dynamic DNA routing table for less memory and fast IP processing. Soft Comput. 1–14 (2020)

    Google Scholar 

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Vijay, M.M., Shalini Punithavathani, D. (2022). A Memory-Efficient Adaptive Optimal Binary Search Tree Architecture for IPV6 Lookup Address. In: Shakya, S., Bestak, R., Palanisamy, R., Kamel, K.A. (eds) Mobile Computing and Sustainable Informatics. Lecture Notes on Data Engineering and Communications Technologies, vol 68. Springer, Singapore. https://doi.org/10.1007/978-981-16-1866-6_57

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