Abstract
The proposed work represents the hardware design and implementation of a median filter that uses architecture, which produces median results hierarchically once data in the sliding window is completely available. The median filter was designed based on the sorting methods; here, it makes use of a non-conventional algorithm where entire sorting of data is not required. The proposed three-value sorter where the parallel comparison of data is done is the fastest method as compared to other methods. The work is implemented in Xilinx Vivado 2016.4 software, and the performance analysis is carried out using Cadence 90 nm technology and with the supply voltage of 0.9 V. Area, power, and delay parameters of the implemented architecture for different filter sizes are computed. The hardware implementation of the median filter architecture is done by using Nexys4 DDR FPGA kit making use of block ROM, block RAM, and clocking wizard. Here, the entire operation is carried out at 25.132 MHz frequency.
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Selvaganesh, M., Vigneswaran, E.E., Vaishnavi, V. (2021). FPGA Implementation of Low Latency and Highly Accurate Median Filter Architecture for Image Processing Applications. In: Suma, V., Chen, J.IZ., Baig, Z., Wang, H. (eds) Inventive Systems and Control. Lecture Notes in Networks and Systems, vol 204. Springer, Singapore. https://doi.org/10.1007/978-981-16-1395-1_59
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DOI: https://doi.org/10.1007/978-981-16-1395-1_59
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