Abstract
With the limitations of CMOS technology scaling, rigorous research of alternate and competent technologies is emerged to impel the boundaries of digital computing. In this article, we proposed a simple, yet power and performance efficient methods of memory implementation. Present research attempts have been faithful to studying and performing these memory implementation techniques. In this article, we addressed the issues and described the current advanced methods of data storage. Conventionally, the WRITE operation in static memory consumes more power than the dynamic power associated with it because of the high-bit line voltage swing during the WRITE operation. This work presents the designing and characterization of ultra-scalable SRAM in terms of power and performance. The simulations are carried out using CMOS technology in cadence tool. The simulation results and functionality are distinguished with conventional memory units.
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We are very grateful to the reviewers for their valuable feedback and advice on further improving the manuscript. I thank the co-authors who have contributed immeasurably in making this manuscript possible, and I offer my sincere gratitude to each of them
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Pasumarty, G.K., Raju, N.V.G., Majji, S. (2021). Obscuring of Data Leakage in Static Memory Cell and Optimization of WRITE Power. In: Mallick, P.K., Bhoi, A.K., Marques, G., Hugo C. de Albuquerque, V. (eds) Cognitive Informatics and Soft Computing. Advances in Intelligent Systems and Computing, vol 1317. Springer, Singapore. https://doi.org/10.1007/978-981-16-1056-1_34
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DOI: https://doi.org/10.1007/978-981-16-1056-1_34
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